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CY7C1524V18-200BZC Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1524V18-200BZC
Description  72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1524V18-200BZC Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY7C1522V18
CY7C1529V18
CY7C1523V18
CY7C1524V18
Document #: 38-05564 Rev. *D
Page 8 of 28
Functional Overview
The
CY7C1522V18,
CY7C1529V18,
CY7C1523V18,
CY7C1524V18 are synchronous pipelined Burst SRAMs
equipped with a DDR-II Separate I/O interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks, C/C (or
K/K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of input clocks (K and
K). All synchronous data outputs (Q[x:0]) pass through output
registers controlled by the rising edge of the output clocks, C/C
(or K/K when in single clock mode). All synchronous control
(R/W, LD, BWS[x:0]) inputs pass through input registers
controlled by the rising edge of the input clock (K).
CY7C1523V18 is described in the following sections. The
same
basic
descriptions
apply
to
CY7C1522V18,
CY7C1529V18, and CY7C1524V18.
Read Operations
The CY7C1523V18 is organized internally as two arrays of
2M
× 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the Address inputs is
stored in the Read address register. Following the next K clock
rise the corresponding lowest-order 18-bit word of data is
driven onto the Q[17:0] using C as the output timing reference.
On the subsequent rising edge of C the next 18-bit data word
is driven onto the Q[17:0]. The requested data will be valid 0.45
ns from the rising edge of the output clock (C or C, or K or K
when in single clock mode, for 250-MHz and 200-MHz
devices). Read accesses can be initiated on every K clock
rise. Doing so will pipeline the data flow such that data is trans-
ferred out of the device on every rising edge of the output
clocks, C/C (or K/K when in single clock mode).
When read access is deselected, the CY7C1523V18 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically tri-state the outputs following the
next rising edge of the positive output clock (C).
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). On the
following K clock rise the data presented to D[17:0] is latched
and stored into the lower 18-bit Write Data register provided
BWS[1:0] are both asserted active. On the subsequent rising
edge of the negative input clock (K), the information presented
to D[17:0] is also stored into the Write Data register provided
BWS[1:0] are both asserted active. Write accesses can be
initiated on every rising edge of input clock (K). Doing so
pipelines the data flow so that 18 bits of data are written into
the device on every rising edge of both input clocks (K and K).
When write access is deselected, the device will ignore all data
inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1523V18. A
Write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1523V18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation. The
echo clocks are synchronized to input clocks K/K in this mode.
DDR Operation
The CY7C1523V18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double DDR mode of operation. If a Read occurs after a
Write cycle, address and data for the Write are stored in
registers. The write information must be stored because the
SRAM can not perform the last word Write to the array without
conflicting with the Read. The data stays in this register until
the next Write cycle occurs. On the first Write cycle after the
Read(s), the stored data from the earlier Write will be written
into the SRAM array. This is called a Posted Write.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5
× the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the Separate I/O DDR. In the single clock mode, CQ is
generated with respect to K and CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC
Timing table.


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