CY7C4211V-15AXI datasheet(10/18 Pages) CYPRESS

Part #	CY7C4211V-15AXI

Description	Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 18 page

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B

Page 10 of 18

Reset Timing[13]

Notes:

13. The clocks (RCLK, WCLK) can be free-running during reset.

14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.

15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable

for the programmable flag offset registers.

Switching Waveforms (continued)

tRS

tRSR

Q0 − Q8

RS

tRSF

OE=1

OE=0

REN1,

REN2

EF,PAE

FF,PAF,

tRSS

tRSR

tRSS

tRSR

tRSS

WEN2/LD

WEN1

[15]

[14]

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