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CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Document #: 38-06013 Rev. *B
Page 8 of 16
Switching Waveforms
Write Cycle Timing
Read Cycle Timing
Notes:
12. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
13. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
tCLKH
tCLKL
NO OPERATION
tDS
tSKEW1
tENS
WEN1
tCLK
tDH
tWFF
tWFF
tENH
WCLK
D0 –D17
FF
REN1, REN2
RCLK
NO OPERATION
WEN2
(if applicable)
[12]
REN1, REN2
tCLKH
tCLKL
NO OPERATION
tSKEW1
WEN1
tCKL
tOHZ
tREF
tREF
RCLK
Q0 –Q17
EF
WCLK
OE
tOE
tENS
tOLZ
tA
tENH
VALID DATA
WEN2
[13]
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