CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B
Page 6 of 29
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B. (Note that when Port B is
configured for a long-word size, the Big Endian function has
no application and the BE input is a “Don’t Care.”
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Port
A to Port B, the most significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the least
significant byte (word) of the long-word written to Port A will be
transferred to Port B last.
A LOW on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Little Endian
arrangement. When data is moving in the direction from Port
A to Port B, the least significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the most
significant byte (word) of the long-word written to Port A will be
transferred to Port B last. After Master Reset, the FWFT select
function is active, permitting a choice between two possible
timing modes: CY Standard Mode or First-Word Fall-Through
(FWFT) Mode. Once the Master Reset (MRS1, MRS2) input
is HIGH, a HIGH on the BE/FWFT input at the second
LOW-to-HIGH transition of CLKA will select CY Standard
Mode. This mode uses the Empty Flag function (EF) to
indicate whether or not there are any words present in the
FIFO memory. It uses the Full Flag function (FF) to indicate
whether or not the FIFO memory has any free space for
writing. In CY Standard Mode, every word read from the FIFO,
including the first, must be requested using a formal read
operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input during the next LOW-to-HIGH transition
of CLKA will select FWFT Mode. This mode uses the Output
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B0–35). It also uses the Input Ready
function (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Two registers in the CY7C436x3 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AE) offset register is labeled X. The Port A
Almost Full flag (AF) offset register is labeled Y. The index of
each register name corresponds with preset values during the
reset of a FIFO, programmed in parallel using the FIFO’s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see Table 2).
To load a FIFO’s Almost Empty flag and Almost Full flag offset
registers with one of the three preset values listed in Table 2,
the Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1, MRS2). For
example, to load the preset value of 64 into X and Y, SPM, FS0
and FS1 must be HIGH when the FIFO reset (MRS1, MRS2)
returns HIGH. When using one of the preset values for the flag
offsets, the FIFO can be reset simultaneously or at different
times.
To program the X and Y registers from Port A, perform a
Master Reset on both FIFOs simultaneously with SPM HIGH
and FS0 and FS1 LOW during the LOW-to-HIGH transition of
MRS1/MRS2. After this reset is complete, the first two writes
to the FIFO do not store data in RAM but load the offset
registers in the order Y and X. The Port A data inputs used by
the offset registers are (A0–9), (A0–11), or (A0–13),for the
CY7C436x3, respectively. The highest numbered input is used
as the most significant bit of the binary number in each case.
Valid programming values for the registers range from 0 to
1023 for the CY7C43643; 0to 4095 for the CY7C43663; 0 to
16383 for the CY7C43683. Before programming the offset
register, FF/IR is set HIGH. FIFOs begin normal operation
after programming is done.
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH
during the LOW-to-HIGH transition of MRS1/MRS2. After this
reset is complete, the X and Y register values are loaded
bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. Twenty,
twenty four, or twenty eight bit writes are needed to complete
the programming for the CY7C436x3, respectively. The two
registers are written in the order Y then finally X. The first-bit
write stores the most significant bit of the Y register and the
last-bit write stores the least significant bit of the X register.
Each register value can be programmed from 0 to 1023 for the
CY7C43643; 0to 4095 for the CY7C43663; 0 to 16383
(Cy7c43683).
When the option to program the offset registers serially is
chosen, the Port A Full/Input Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the
LOW-to-HIGH transition of CLKA after the last bit is loaded to
allow normal FIFO operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active mail 2
register outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0–35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see
Table 3). FIFO writes on Port A are independent of any
concurrent Port B operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read Select (W/RB) is the
inverse of the Port A Write/Read Select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read Select (W/RB). The B0–35
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