CY7C43644
CY7C43664
CY7C43684
Document #: 38-06022 Rev. *B
Page 9 of 39
Almost Empty flag and Almost Full flag offset programming
above). An Almost Full flag is LOW when the number of words
in its FIFO is greater than or equal to (1024–Y), (4096–Y), or
(16384–Y) for the CY7C436X4 respectively. An Almost Full
flag is HIGH when the number of words in its FIFO is less than
or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for
the CY7C436X4 respectively.[2]
Two LOW-to-HIGH transitions of the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096/16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0–35 data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
employs data lines A0–35. If the selected Port A bus size is 18
bits, then the usable width of the Mail1 Register employs data
lines A0–17. (In this case, A18–35 are “Don’t Care” inputs.) If the
selected Port A bus size is 9 bits, then the usable width of the
Mail1 Register employs data lines A0–8. (In this case, A9–35 are
“Don’t Care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0–35 data to the
Mail2 Register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employs data lines B0–35. If the selected Port B bus size is 18
bits, then the usable width of the Mail2 Register employs data
lines B0–17. (In this case, B18–35 are “don’t care” inputs.) If the
selected Port B bus size is 9 bits, then the usable width of the
Mail2 Register employs data lines B0–8. (In this case, B9–35 are
“don’t care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, W/RB, and ENB with MBB HIGH. For a
36-bit bus size, 36 bits of mailbox data are placed on B0–35.
For an 18-bit bus size, 18 bits of mailbox data are placed on
B0–17. (In this case, B18–35 are indeterminate.) For a 9-bit bus
size, 9 bits of mailbox data are placed on B0–8. (In this case,
B9–35 are indeterminate.)
The Mail2 register Flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selected by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0–17. (In this case, A18–35 are indeterminate.) For
a 9-bit bus size, 9 bits of mailbox data are placed on A0–8. (In
this case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be configured in a 36-bit long-word, 18-bit
word, or 9-bit byte format for data read from FIFO1 or written
to FIFO2. The levels applied to the Port B Bus Size Select
(SIZE) and the Bus Match Select (BM) determine the Port B
bus size. These levels should be static throughout FIFO
operation. Both bus size selections are implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either
byte-or word-size. They are referred to as Big Endian (most
significant byte first) and Little Endian (least significant byte
first). The level applied to the Big Endian Select (BE) input
during the LOW-to-HIGH transition of MRS1 and MRS2
selects the endian method that will be active during FIFO
operation. BE is a don’t care input when the bus size selected
for Port B is long word. The endian method is implemented at
the completion of Master Reset, by the time the Full/Input
ready flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7C436X4. Bus-matching operations
are done after data is read from the FIFO1 RAM and before
data is written to the FIFO2 RAM. These bus-matching opera-
tions are not available when transferring data via mailbox
registers. Furthermore, both the word- and byte-size bus
selections limit the width of the data bus that can be used for
mail register operations. In this case, only those byte lanes
belonging to the selected word- or byte-size bus can carry
mailbox data. The remaining data outputs will be indeter-
minate. The remaining data inputs will be “don’t care” inputs.
For example, when a word-size bus is selected, then mailbox
data can be transmitted only between A0–17 and B0–17. When
a byte-size bus is selected, then mailbox data can be trans-
mitted only between A0–8 and B0–8.
Bus-Matching FIFO1 Reads
Data is read from the FIFO1 RAM in 36-bit long-word incre-
ments. If a long-word bus size is implemented, the entire
long-word immediately shifts to the FIFO1 output register. If
byte or word size is implemented on Port B, only the first one
or two bytes appear on the selected portion of the FIFO1
output register, with the rest of the long-word stored in auxiliary
registers. In this case, subsequent FIFO1 reads output the rest
of the long-word to the FIFO1 output register.
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