CY7C1524V18-300BZXC datasheet(10/28 Pages) CYPRESS

Part #	CY7C1524V18-300BZXC

Description	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 28 page

CY7C1522V18

CY7C1529V18

CY7C1523V18

CY7C1524V18

Document #: 38-05564 Rev. *D

Page 10 of 28

Write Cycle Descriptions (CY7C1522V18 and CY7C1523V18) [3, 9]

BWS0/NWS0 BWS1/NWS1

KK

Comments

L

L-H

–

During the Data portion of a Write sequence

:

CY7C1522V18

− both nibbles (D

[7:0]) are written into the device,

CY7C1523V18

− both bytes (D

[17:0]) are written into the device.

L

–

L-H

During the Data portion of a Write sequence

:

CY7C1522V18

− both nibbles (D

[7:0]) are written into the device,

CY7C1523V18

− both bytes (D

[17:0]) are written into the device.

L

H

L-H

–

During the Data portion of a Write sequence

:

CY7C1522V18

− only the lower nibble (D

[3:0]) is written into the device. D[7:4] will

remain unaltered,

CY7C1523V18

− only the lower byte (D

[8:0]) is written into the device. D[17:9] will

remain unaltered.

L

H

–

L-H

During the Data portion of a Write sequence

:

CY7C1522V18

− only the lower nibble (D

[3:0]) is written into the device. D[7:4] will

remain unaltered,

CY7C1523V18

− only the lower byte (D

[8:0]) is written into the device. D[17:9] will

remain unaltered.

H

L

L-H

–

During the Data portion of a Write sequence

:

CY7C1522V18

− only the upper nibble (D

[7:4]) is written into the device. D[3:0] will

remain unaltered,

CY7C1523V18

− only the upper byte (D

[17:9]) is written into the device. D[8:0] will

remain unaltered.

H

L

–

L-H

During the Data portion of a Write sequence

:

CY7C1522V18

− only the upper nibble (D

[7:4]) is written into the device. D[3:0] will

remain unaltered,

CY7C1523V18

− only the upper byte (D

[17:9]) is written into the device. D[8:0] will

remain unaltered.

H

L-H

–

No data is written into the devices during this portion of a Write operation.

H

–

L-H

No data is written into the devices during this portion of a Write operation.

Note:

9. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1522V18 and CY7C1523V18 and also BWS2,

BWS3 in the case of CY7C1524V18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.

Similar Part No. - CY7C1524V18-300BZXC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1524AV18	1Mb / 28P	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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Similar Description - CY7C1524V18-300BZXC

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Cypress Semiconductor	CY7C1522AV18	686Kb / 30P	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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	CY7C1422AV18	466Kb / 28P	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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CY7C1524V18-300BZXC Datasheet(PDF) 10 Page - Cypress Semiconductor

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