CY7C68000
Document #: 38-08016 Rev. *H
Page 5 of 14
56
49
D0
I/O
Bidirectional Data Bus. This bidirectional bus is used as the entire data
bus in the 8-bit bidirectional mode or the least significant eight bits in the 16-
bit mode or under the 8-bit unidirectional mode these bits are used as inputs
for data, selected by the RxValid signal.
55
48
D1
I/O
53
46
D2
I/O
51
44
D3
I/O
50
43
D4
I/O
48
41
D5
I/O
46
39
D6
I/O
45
38
D7
I/O
44
37
D8
I/O
Bidirectional Data Bus. This bidirectional bus is used as the upper eight
bits of the data bus when in the 16-bit mode, and not used when in the 8-bit
bidirectional mode. Under the 8-bit unidirectional mode these bits are used
as outputs for data, selected by the TxValid signal.
43
36
D9
I/O
41
34
D10
I/O
40
33
D11
I/O
38
31
D12
I/O
36
29
D13
I/O
34
27
D14
I/O
33
26
D15
I/O
1
50
CLK
Output
Clock. This output is used for clocking the receive and transmit parallel data
on the D[15:0] bus.
10
3
Reset
Input
N/A
Active HIGH Reset. Resets the entire chip. This pin can be tied to VCC
through a 0.1
μF capacitor and to GND through a 100 K resistor for a 10
msec RC time constant.
19
12
XcvrSelect
Input
N/A
Transceiver Select. This signal selects between the Full Speed (FS) and
the High Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
20
13
TermSelect
Input
N/A
Termination Select. This signal selects between the between the Full
Speed (FS) and the High Speed (HS) terminations:
0: HS termination
1: FS termination
9
2
Suspend
Input
N/A
Suspend. Places the CY7C68000 in a mode that draws minimal power from
supplies. Shuts down all blocks not necessary for Suspend/Resume opera-
tions. While suspended, TermSelect must always be in FS mode to ensure
that the 1.5 K ohm pull-up on DPLUS remains powered.
0: CY7C68000 circuitry drawing suspend current
1: CY7C68000 circuitry drawing normal current
26
19
LineState1
Output
Line State. These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
25
18
LineState0
Output
Line State. These signals reflect the current state of the single-ended
receivers. They are combinatorial until a ‘usable’ CLK is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
00–0: SE0
01–1: ‘J’ State
10–2: ‘K’ State
11–3: SE1.
Table 5-1. Pin Descriptions (continued)[1]
SSOP QFN
Name
Type
Default
Description
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