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CY8C41123 and CY8C41223
PRELIMINARY
Document 001-00360 Rev. *A
Page 8 of 36
6.1.3
32-Pin QFN Part Pinouts
The 32-pin QFN part is for the CY8C41000 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
32-Pin OCD Part Pinout (QFN**)
Pin
No.
Name
Description
CY8C41000 OCD PSoC Device
Not for Production
1
NC
No Connection
2
NC
No Connection
3OCD
HCLK
On-Chip Debug Clock
4OCD
CCLK
On-Chip Debug Clock
5
IO
I
P0[7]
I2C Clock
6
IO
I
P0[5]
I2C Data
7
IO
I
P0[3]
8
IO
I
P0[1]
9
NC
No Connection
10
NC
No Connection
11
IO
I
P1[1]
I2C Clock*
12
Power
Vss
13
IO
I
P1[0]
I2C Data*
14
NC
No Connection
15
NC
No Connection
16
NC
No Connection
17
IO
I
P0[0]
18
IO
I
P0[2]
Optional External CLK Input (EXTCLK)
19
IO
I
P0[4]
20
IO
I
P0[6]
21
I
XRES
External Reset
22
OCD
OCDO On-Chip Debug Data
23
OCD
OCDE On-Chip Debug Data
24
NC
No Connection
25
DNU
Do Not Use
26
HVI
VS0
High Voltage Sense 0
27
HVO
HVO
GD0
High Side Gate Driver 0
28
Power
HVdd
Supply Voltage
29
Power
HVdd
Supply Voltage
30
HVO
HVO
GD1
High Side Gate Driver 1
31
HVI
VS1
High Voltage Sense 1
32
NC
No Connection
CP
Power
Vss
Center Pad Must be Connected to Ground
LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage, NC = No Connection, OCD = On-Chip Debug.
* These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details.
** The QFN package has a center pad that must be connected to ground (Vss).
NC
NC
HCLK
CCLK
P0[7]
P0[5]
QFN
(T op View)
(CP)
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P0[3]
P0[1]
NC
OCDE
P0[2]
P0[0]
OCDO
XRES
P0[6]
P0[4]
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