CY8C42323/CY8C42423
PRELIMINARY
CY8C42123/CY8C42223
Document 38-12034 Rev. *C
Page 2 of 42
3.0
Complete Feature List
• Extended Operating Voltage of 2.5V to 36V
• Powerful Harvard Architecture Processor
— M8C Processor Speeds to 24 MHz
— Low Power at High Speed
— Industrial Temperature Range: -40°C to +85°C
• Additional Flexibility for Sleep Modes
— Select when System Resources are Shut Down
— Very Low Current Mode for 100 nA Sleep (Deep Sleep)
• 2 Advanced Power PSoC Blocks
— 2 High Voltage Analog Sense Inputs
— 2 High Voltage Linear Opamp Control Loops for Driving
Power PFETs
— 2 High Voltage Switching Control Loops for Driving Ex-
ternal PFETs
— 2 High Voltage CMOS or Open Drain Outputs
• Advanced Analog Blocks
— Analog Absolute Accuracy (0.75%)
— 2 Comparators with DAC References
— 6- to 12-Bit ADC (20 Ksps at 8 Bits)
— Configurable Analog Mux, 10:1 or 5:2 Differential
• 4 Advanced Digital Blocks (2 with Integrated Deadband)
— 8- to 16-Bit Timers, Counters, and PWMs
— Connectable to All GPIO Pins
— Connectable to All High Voltage Output (HVO) Pins
— Single Block Deadband PWM with Kill
— Digital Blocks can Drive Outputs to 36V
— Complex Peripherals by Combining Blocks
• Flexible On-Chip Memory
— 4KB Flash Program Storage 50,000 Erase/Write Cycles
— 256 Bytes SRAM
— In-System Serial Programming (ISSP
™)
— Partial Flash Updates (64-Byte Blocks)
— Flexible Protection Modes
— EEPROM Emulation in Flash
• Precision, Programmable Clocking
• Development Tools
— Free Development Software
(PSoC™ Designer)
— Full-Featured, In-Circuit Emulator and
Programmer
— Full Speed Emulation
— Complex Breakpoint Structure
— 128KB Trace Memory
— Free Application Generation Software
(PSoC Express™)
• Additional System Resources
— I2C™ Master, Slave, and Multi-Master to 400 kHz
— Watchdog and Sleep Timers
— User-Configurable Low Voltage Detection
— Integrated Supervisory Circuit
— On-Chip Precision Voltage Reference
— 4-Bit Current References
4.0
PSoC Functional Overview
The key feature set of the Power PSoC family is the ability to
be powered from and connect to voltages above the standard
5V logic voltage used by most microcontrollers. The Power
PSoC's HVdd pin can connect to a supply voltage of up to 36V.
Internally, an LDO regulator converts the supply voltage to 5V
for powering the analog system, digital system, the core, and
the GPIO.
High voltage signals can be connected to the analog circuitry
through one of two selectable attenuators, each having three
ranges. These precision dividers reduce the external analog
voltage by a factor of 4, 8, or 16. This allows single-ended or
differential signals with up to 36V common mode to be
measured with the ADC. The GPIO pins are not high-voltage
tolerant. Signals with voltages exceeding VGPIO (as shown in
the Absolute Maximum Ratings table, Table 8.2) cannot be
connected to the GPIO pins (P0 [7:0] and P1 [1:0]). Doing so
will damage the device.
The Power PSoC family consists of several Mixed-Signal
Array with On-Chip Controller devices. These devices are
designed to replace multiple traditional MCU-based system
components with one, low-cost single-chip programmable
component. A Power PSoC device includes configurable
analog, digital, and power blocks, as well as programmable
interconnects. This architecture allows the user to create
customized peripheral configurations, to match the require-
ments of each individual application. Additionally, a fast CPU,
Flash program memory, SRAM data memory, and config-
urable IO are included in a range of convenient pinouts.
The PSoC architecture, as illustrated in Figure 2-1, is
comprised of five main areas: the Core, the System
Resources, the Digital System, the Analog System, and the
Power Control System. Configurable global bus resources
allow all the device resources to be combined into a complete
custom system. Each PSoC device includes 4 digital blocks,
up to 2 digital high voltage outputs, and up to 10 general
purpose IO (GPIO). The GPIO provide access to the global
digital and analog interconnects.
4.1
Power PSoC Core
The Power PSoC Core is a powerful engine that supports a
rich instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low-speed oscil-
lator). The CPU core, called the M8C, is a powerful processor
with speeds up to 24 MHz. The M8C is a four MIPS 8-bit
Harvard architecture microprocessor.
System Resources provide additional capability, such as
digital clocks for increased flexibility of the PSoC mixed-signal
arrays; I2C functionality for implementing master, slave, and
multi-master; an internal voltage reference of 1.3V for a
number of analog PSoC subsystems; and various system
resets supported by the M8C.
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