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| CY14B101K_0711 |
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 CYPRESS
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6 page 
CY14B101K Document Number: 001-06401 Rev. *G Page 6 of 24 Low Average Active Power CMOS technology provides the CY14B101K the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Cycle Time. The worst case current consumption is shown for commercial temperature range, VCC = 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14B101K depends on the following items: ■ The duty cycle of chip enable ■ The overall cycle rate for accesses ■ The ratio of READs to WRITEs ■ The operating temperature ■ The VCC level ■ IO loading Real Time Clock Operation nvTIME Operation The CY14B101K offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. Internal double buffering of the clock and the clock or timer information registers prevents accessing transitional internal clock data during a READ or WRITE operation. Double buffering also circumvents disrupting normal timing counts or clock accuracy of the internal clock while accessing clock data. Clock and Alarm Registers store data in BCD format. Clock Operations The clock registers maintain time up to 9,999 years in one second increments. The user sets the time to any calendar time and the clock automatically keeps track of days of the week, month, leap years, and century transitions. There are eight registers dedicated to the clock functions that are used to set time with a WRITE cycle and to READ time during a READ cycle. These registers contain the Time of Day in BCD format. Bits defined as ‘0’ are currently not used and are reserved for future use by Cypress. Reading the Clock While the double buffered RTC register structure reduces the chance of reading incorrect data from the clock, halt internal updates to the CY14B101K clock registers before reading clock data to prevent the reading of data in transition. Stopping the internal register updates does not affect clock accuracy. The update process is stopped by writing a ‘1’ to the READ bit ‘R’ (in the flags register at 0x1FFF0) and does not restart until a ‘0’ is written to the READ bit. The RTC registers then READ when the internal clock continues to run. Within 20 ms after a ‘0’ is written to the READ bit, all CY14B101K registers are simultaneously updated. Setting the Clock Setting the WRITE bit ‘W’ (in the flags register at 0x1FFF0) to a ‘1’ halts updates to the CY14B101K registers. The correct day, date, and time are then written into the registers in 24 hour BCD format. The time written is referred to as the ‘Base Time’. This value is stored in nonvolatile registers and used in calculation of the current time. Resetting the WRITE bit to ‘0’ transfers those values to the actual clock counters, after which the clock resumes normal operation. Backup Power The RTC in the CY14B101K is intended for permanently powered operations. Either the VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH, the device switches to the backup power supply. The clock oscillator uses very little current to maximize the backup time available from the backup source. Regardless of clock operation with the primary source removed, the data stored in nvSRAM is secure, as it is stored in the nonvolatile elements when power was lost. During backup operation, the CY14B101K consumes a maximum of 300 nA at 2V. According to the application, the user chooses the capacitor or battery values. Backup time values, based on maximum current specifications, are shown in the following table. Nominal times are approxi- mately three times longer. Figure 3. Current vs. Cycle Time Table 2. RTC Backup Time Capacitor Value Backup Time 0.1F 72 hours 0.47F 14 days 1.0F 30 days |
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