CY14B101K_0711 datasheet(3/24 Pages) CYPRESS | 1 Mbit (128K x 8) nvSRAM With Real Time Clock

3 page

CY14B101K

Document Number: 001-06401 Rev. *G

Page 3 of 24

Device Operation

The CY14B101K nvSRAM is made up of two functional compo-

nents paired in the same physical cell, a SRAM memory cell, and

a nonvolatile QuantumTrap cell. The SRAM memory cell

operates as a standard fast static RAM. Data transfers from the

SRAM to the nonvolatile cell (the STORE operation) or from the

nonvolatile cell to SRAM (the RECALL operation). This unique

architecture enables all cells to store and recall in parallel. During

the STORE and RECALL operations, SRAM READ and WRITE

operations are inhibited. The CY14B101K supports infinite reads

and writes similar to a typical SRAM. In addition, it provides

infinite RECALL operations from the nonvolatile cells and up to

200,000 STORE operations.

SRAM READ

The CY14B101K performs a READ cycle whenever CE and OE

are LOW, when WE and HSB are HIGH. The address specified

on pins A0-16 determines which of the 131,072 data bytes are

accessed. When the READ is initiated by an address transition,

the outputs are valid after a delay of tAA (READ cycle 1). If the

READ is initiated by CE or OE, the outputs are valid at tACE or at

tDOE, whichever is later (READ cycle 2). The data outputs

repeatedly respond to address changes within the tAA access

time without the need for transitions on any control input pins. It

remains valid until another address change or until CE or OE is

brought HIGH, or WE or HSB is brought LOW.

SRAM WRITE

A WRITE cycle is performed whenever CE and WE are LOW and

HSB is HIGH. The address inputs must be stable before entering

the WRITE cycle and must remain stable until either CE or WE

go HIGH at the end of the cycle. The data on the common IO pins

DQ0–7 is written into the memory if the data is valid tSD before

the end of a WE controlled WRITE or before the end of an CE

controlled WRITE. Keep OE HIGH during the entire WRITE cycle

to avoid data bus contention on common IO lines. If OE is left

LOW, internal circuitry turns off the output buffers tHZWE after WE

goes LOW.

AutoStore Operation

The CY14B101K stores data to nvSRAM using one of three

storage operations:

1. Hardware Store activated by HSB

2. Software Store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap

technology and is enabled by default on the CY14B101K.

During normal operations, the device draws current from VCC to

charge a capacitor connected to the VCAP pin. This stored

charge is used by the chip to perform a single STORE operation.

If the voltage on the VCC pin drops below VSWITCH, the part

automatically disconnects the VCAP pin from VCC. A STORE

operation is initiated with power provided by the VCAP capacitor.

Figure 2 shows the proper connection of the storage capacitor

(VCAP) for automatic store operation. Refer to the section “DC

Electrical Characteristics” on page 14 for the size of VCAP. The

voltage on the VCAP pin is driven to 5V by a charge pump internal

to the chip. A pull up is placed on WE to hold it inactive during

power up.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware Store operations are ignored unless at least one

WRITE operation takes place since the most recent STORE or

RECALL cycle. Software initiated STORE cycles are performed

regardless of whether a WRITE operation took place. Monitor the

HSB signal by the system to detect if an AutoStore cycle is in

progress.

Hardware STORE (HSB) Operation

The CY14B101K provides the HSB pin for controlling and

acknowledging the STORE operations. Use the HSB pin to

request a hardware STORE cycle. When the HSB pin is driven

LOW, the CY14B101K conditionally initiates a STORE operation

after tDELAY. An actual STORE cycle only begins if a WRITE to

the SRAM has taken place since the last STORE or RECALL

cycle. The HSB pin also acts as an open drain driver that is inter-

nally driven LOW to indicate a busy condition while the STORE

(initiated by any means) is in progress.

SRAM READ and WRITE operations that are in progress when

HSB is driven LOW by any means are given time to complete

before the STORE operation is initiated. After HSB goes LOW,

the CY14B101K continues SRAM operations for tDELAY. During

tDELAY, multiple SRAM READ operations take place. If a WRITE

is in progress when HSB is pulled LOW, it is allowed a time,

tDELAY, to complete. However, any SRAM WRITE cycles

requested after HSB goes LOW are inhibited until HSB returns

HIGH.

During any STORE operation, regardless of how it is initiated,

the CY14B101K continues to drive the HSB pin LOW, releasing

it only when the STORE is complete. After completing the

STORE operation, the CY14B101K remains disabled until the

HSB pin returns HIGH. Leave the HSB unconnected if it is not

used.

Figure 2. AutoStore Mode

VCC

VCAP

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