PRELIMINARY
CY14B104L, CY14B104N
Document #: 001-07102 Rev. *F
Page 10 of 22
AutoStore/Power Up RECALL
Parameters
Description
CY14B104L/CY14B104N
Unit
Min
Max
tHRECALL
[14]
Power Up RECALL Duration
20
ms
tSTORE
[15]
STORE Cycle Duration
15
ms
VSWITCH
Low Voltage Trigger Level
2.65
V
tVCCRISE
VCC Rise Time
150
μs
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[16, 17]
Parameters
Description
15ns
25ns
45ns
Unit
Min
Max
Min
Max
Min
Max
tRC
STORE/RECALL Initiation Cycle Time
15
25
45
ns
tAS
Address Setup Time
0
0
0
ns
tCW
Clock Pulse Width
12
20
30
ns
tGHAX
Address Hold Time
1
1
1
ns
tRECALL
RECALL Duration
100
100
100
μs
tSS
[18, 19]
Soft Sequence Processing Time
70
70
70
μs
Hardware STORE Cycle
Parameters
Description
CY14B104L/CY14B104N
Unit
Min
Max
tDELAY
[20]
Time allowed to complete SRAM Cycle
1
70
μs
tHLHX
Hardware STORE Pulse Width
15
ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[10, 11, 21]
tRC
tAA
tOHA
ADDRESS
DQ (DATA OUT)
DATA VALID
Notes
14. tHRECALL starts from the time VCC rises above VSWITCH.
15. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.
16. The software sequence is clocked with CE controlled or OE controlled reads.
17. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.
18. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.
19. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command
20. Read and write cycles are in progress before HSB are supplied this amount of time to complete.
21. HSB must remain HIGH during READ and WRITE cycles.
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
