PRELIMINARY
CY9C62256
Document# : 38-15001 Rev. *F
Page 2 of 11
Overview
The CY9C62256 is a byte wide MRAM memory. The memory
array is logically organized as 32,768 x 8 and is accessed
using an industry standard parallel asynchronous SRAM-like
interface. The CY9C62256 is inherently nonvolatile and offers
write protect during sudden power loss. Functional operation
of the MRAM is similar to SRAM-type devices, otherwise.
Memory Architecture
Users access 32,768 memory locations each with eight data
bits through a parallel interface. Internally, the memory array
is organized into eight blocks of 512 rows x 64 columns each.
The access and cycle time are the same for read and write
memory operations. Unlike an EEPROM or Flash, it is not
necessary to poll the device for a ready condition since writes
occur at bus speed.
Memory Operation
The CY9C62256 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the MRAM performance is superior. For users
familiar with EEPROM, Flash and FeRAM, the obvious differ-
ences result from higher write performance of MRAM
technology and much higher write endurance.
All memory array bits are set to logic “1” at the time of
shipment.
Read Operation
A read cycle begins whenever WE (Write Enable bar) is
inactive (HIGH) and CE (Chip Enable bar) and OE (Output
Enable bar) are active LOW. The unique address specified by
the 15 address inputs (A0–A14) defines which of the 32,768
bytes of data is to be accessed. Valid data will be available at
the eight output pins within tAA (access time) after the last
address input is stable, providing that CE and OE access times
are also satisfied. If CE and OE access times are not satisfied
then the data access must be measured from the
later-occurring signal (CE or OE) and the limiting parameter is
either tACE for CE or tDOE for the OE rather than address
access.
Write Cycle
The CY9C62256 initiates a write cycle whenever the WE and
CE signals are active (LOW) after address inputs are stable.
The later occurring falling edge of CE or WE will determine the
start of the write cycle. The write cycle is terminated by the
earlier rising edge of CE or WE. All address inputs must be
kept valid throughout the write cycle. The OE control signal
should be kept inactive (HIGH) during write cycles to avoid bus
contention. However, if the output drivers are enabled (CE and
OE active) WE will disable the outputs in tHZWE from the WE
falling edge.
Unlike other nonvolatile memory technologies, there is no
write delay with MRAM. The entire memory operation occurs
in a single bus cycle. Therefore, any operation including read
or write can occur immediately following a write. Data Polling,
a technique used with EEPROMs to determine if the write is
complete is unnecessary. Page write, a technique used to
enhance EEPROM write performance is also unnecessary
because of inherently fast write cycle time for MRAM.
The total Write time for the entire 256K array is 2.3 ms.
Write Inhibit and Data Retention Mode
This feature protects against the inadvertent write. The
CY9C62256 provides full functional capability for VCC greater
than 4.5V and write protects the device below 4.0V. Data is
maintained in the absence of VCC. During the power-up,
normal operation can resume 20
µs after VPFD is reached.
Refer to page 8 for details.
Sudden Power Loss—“Brown Out”
The nonvolatile RAM constantly monitors VCC. Should the
supply voltage decay below the operating range, the
CY9C62256 automatically write-protects itself, all inputs
become don’t care, and all outputs become high-impedance.
Refer to page 8 for details.
Silicon Signature/Device ID
An extra 64 bytes of MRAM are available to the user for Device
ID. By raising A9 to VCC + 2.0V and by using address locations
00(Hex) to 3F(Hex) on address pins A7, A6, A14, A13, A12
and A0 (MSB to LSB) respectively, the additional Bytes may
be accessed in the same manner as the regular memory array,
with 140 ns access time. Dropping A9 from input high
(VCC + 2.0V) to < VCC returns the device to normal operation
after 140-ns delay.
All User Space bits above are set to logic “1” at the time of
shipment.
Magnetic Shielding
CY9C62256 is protected from external magnetic fields through
the application of a “magnetic shield” that covers the entire
memory array.
Applications
Battery-Backed SRAM (BB SRAM) Replacement
CY9C62256 is designed to replace (plug and play) existing
BBSRAM while eliminating the need for battery and VCC
monitor IC, reducing cost and board space and improving
system reliability.
The cost associated with multiple components and assemblies
and manufacturing overhead associated with battery-backed
SRAM is eliminated by using monolithic MRAM. CY9C62256
eliminates multiple assemblies, connectors, modules, field
maintenance and environmental issues common with BB
SRAM. MRAM is a true nonvolatile RAM with high perfor-
mance, high endurance, and data retention.
Battery-backed SRAMs are forced to monitor VCC in order to
switch to the backup battery. Users that are modifying existing
designs to use MRAM in place of BB SRAM, can eliminate the
VCC controller IC along with the battery. MRAM performs this
function on chip.
Cost: The cost of both the component and manufacturing
overhead of battery-backed SRAM is high. In addition, there is
a built in rework step required for battery attachment in case
Address (MSB to LSB)
A7 A6 A14 A13 A12 A0
Description
ID
00h
Manufacturer ID
34h
01h
Device ID
40h
02h – 3Fh
User Space
62 Bytes
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