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CY14E064L
Document Number: 001-06543 Rev. *D
Page 10 of 17
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [10,11]
Parameter
Description
25 ns Part
45 ns Part
Unit
Min
Max
Min
Max
tRC
STORE/RECALL Initiation Cycle Time
25
45
ns
tAS
Address Setup Time
0
0
ns
tCW
Clock Pulse Width
20
30
ns
tGLAX
Address Hold Time
20
20
ns
tRECALL
RECALL Duration
20
20
μs
Hardware STORE Cycle
Parameter
Description
CY14E064L
Unit
Min
Max
tSTORE
[6]
STORE Cycle Duration
10
ms
tDELAY
[12]
Time Allowed to Complete SRAM Cycle
1
μs
tRESTORE
[13]
Hardware STORE High to Inhibit Off
700
ns
tHLHX
Hardware STORE Pulse Width
15
ns
tHLBL
Hardware STORE Low to STORE Busy
300
ns
Notes
10. The software sequence is clocked with CE controlled READs.
11. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
12. Read and Write cycles in progress before HSB are given this amount of time to complete.
13. tRESTOREis only applicable after tSTORE is complete.
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