CY23EP09
Document #: 38-07760 Rev. *B
Page 5 of 13
tLOCK
PLL Lock Time[9]
Stable power supply, valid clocks presented on
REF and CLKOUT pins
––
1.0
ms
TJCC
[9,10]
Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF
–
25
55
ps
3.3V supply, >66 MHz, <30 pF, standard drive
–
65
125
ps
3.3V supply, >66 MHz, <30 pF, high drive
–
53
100
ps
2.5V supply, >66 MHz, <15 pF, standard drive
–
35
95
ps
2.5V supply, >66 MHz, <15 pF, high drive
–
30
65
ps
2.5V supply, >66 MHz, <30 pF, high drive
–
75
145
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive
–
16
–
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, high drive
–
14
–
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive
–
23
–
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, high drive
–
22
–
ps
TPER
[9,10]
Period Jitter, Peak
3.3V supply, 66–100 MHz, <15 pF
–
20
75
ps
3.3V supply, >100 MHz, <15 pF
–
15
45
ps
3.3V supply, >66 MHz, <30 pF, standard drive
–
40
100
ps
3.3V supply, >66 MHz, <30 pF, high drive
–
30
70
ps
2.5V supply, >66 MHz, <15 pF, standard drive
–
25
60
ps
2.5V supply, 66–100 MHz, <15 pF, high drive
–
25
60
ps
2.5V supply, >100 MHz, <15 pF, high drive
–
15
45
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive
–
28
–
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, high drive
–
24
–
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive
–
40
–
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, high drive
–
37
–
ps
Note:
10. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may
be found in the application note “Understanding Data Sheet Jitter Specifications for Cypress Clock Products.”
3.3V and 2.5V AC Electrical Specifications (continued)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
Switching Waveforms
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
All Outputs Rise/Fall Time
OUTPUT
t3
3.3V(2.5V)
0V
0.8V(0.6V)
2.0V(1.8V)
2.0V(1.8V)
0.8V(0.6V)
t4