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CY23FP12-002
Document #: 38-07644 Rev. **
Page 8 of 10
ttsk
Tracking Skew
Input reference clock @ < 50-KHz modulation
with ±3.75% spread
200
ps
tLOCK
PLL Lock Time[5]
Stable power supply, valid clock at REF
1.0
ms
TLD
Inserted Loop Delay
Max loop delay for PLL Lock (stable
frequency)
7ns
Max loop delay to meet Tracking Skew Spec
4
ns
Switching Characteristics for CY23FP12-002SC/I [5]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
OUTPUT
t3
3.3V
0V
0.8V
2.0V
2.0V
0.8V
t4
All Outputs Rise/Fall Time
Output-Output Skew
1.4V
t5
OUTPUT
OUTPUT
1.4V
Input-Output Propagation Delay
VDD/2
t6
INPUT
FBK
VDD/2
VDD/2
VDD/2
t7
FBK, Device 1
FBK, Device 2
Device-Device Skew
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