CY14B101K
Document Number: 001-06401 Rev. *G
Page 7 of 24
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, use a 3V lithium and the CY14B101K only source
current from the battery when the primary power is removed.
However, the battery does not recharge at any time by the
CY14B101K. The battery capacity is chosen for total anticipated
cumulative downtime required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFF8 controls
the starting and stopping of the oscillator. This bit is nonvolatile
and is shipped to customers in the “enabled” (set to ‘0’) state. To
preserve battery life when the system is in storage, OSCEN is
set to a ‘1’. This turns off the oscillator circuit extending the
battery life. If the OSCEN bit goes from disabled to enabled, it
takes approximately 5 seconds (10 seconds max) for the
oscillator to start.
The CY14B101K has the ability to detect oscillator failure. This
is recorded in the OSCF (Oscillator Failed bit) of the Flags
register at address 0x1FFF0. When the device is powered on
(VCC goes above VSWITCH) the OSCEN bit is checked for
“enabled” status. If the OSCEN bit is enabled and the oscillator
is not active, the OSCF bit is set. The user must check for this
condition and then WRITE a ‘0’ to clear the flag. In addition to
setting the OSCF flag bit, the time registers are reset to the “Base
Time” (see the section “Setting the Clock” on page 6): the value
that is last written to the time keeping registers. The Control or
Calibration register and the OSCEN bit are not affected by the
oscillator failed condition.
If the voltage on the backup supply (either VRTCcap or VRTCbat)
falls below their minimum level, the oscillator may fail. This may
lead to the oscillator failed condition that is detected when
system power is restored.
The value of OSCF is reset to ‘0’ when the time registers are
written for the first time. This initializes the state of this bit that is
set when the system is first powered on.
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal usually specified to 35 ppm limits at 25°C. This error
equates to +1.53 minutes in accordance with the month. The
CY14B101K employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25°C. The calibration circuit adds or
subtracts counts from the oscillator divider circuit.
The number of pulses that are suppressed (subtracted, negative
calibration) or split (added, positive calibration) depends upon
the value loaded into the five calibration bits found in calibration
register at 0x1FFF8. Adding counts speeds the clock up and
subtracting counts slows the clock down. The calibration bits
occupy the five lower order bits in the Control register 8. Set
these bits to represent any value between 0 and 31 in binary
form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration
and a ‘0’ indicates negative calibration. Calibration occurs within
a 64 minute cycle. The first 62 minutes in the cycle may, once in
accordance with minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles.
If a binary ‘1’ is loaded into the register, only the first two minutes
of the 64 minute cycle are modified. If a binary 6 is loaded, the
first 12 are affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles
for every 125, 829,120 actual oscillator cycles, that is, 4.068 or
–2.034 ppm of adjustment in accordance with calibration step in
the calibration register.
To determine how to set the calibration one may set the CAL bit
in the flags register at 0x1FFF0 to ‘1’ that causes the INT pin to
toggle at a nominal 512 Hz. Any deviation measured from the
512 Hz indicates the degree and direction of the required
correction. For example, a reading of 512.010124 Hz indicates
a +20 ppm error, requiring to load a –10 (001010) into the
Calibration register. Note that setting or changing the calibration
register does not affect the frequency test output frequency.
Alarm
The alarm function compares user programmed values to the
corresponding time-of-day values. When a match occurs, the
alarm event occurs. The alarm drives an internal flag, AF, and
may drive the INT pin if required.
There are four alarm match fields. They are date, hours, minutes,
and seconds. Each of these fields also has a match bit that is
used to determine if the field is used in the alarm match logic.
Setting the match bit to ‘0’ indicates that the corresponding field
is used in the match process.
Depending on the match bits, the alarm occurs as specifically as
one particular second on one day of the month or as frequently
as once in accordance with second continuously. The MSb of
each alarm register is a match bit. Selecting none of the match
bits (all 1s) indicates that no match is required. The alarm occurs
every second. Setting the match select bit for seconds to ‘0’
causes the logic to match the seconds alarm value to the current
time of day. Since a match occurs for only one value in
accordance with minute, the alarm occurs once in accordance
with minute. Likewise, setting the seconds and minutes match
bits causes an exact match of these values. Thus, an alarm
occurs once in accordance with hour. Setting seconds, minutes,
and hours causes a match once in accordance with day. Lastly,
selecting all match values causes an exact time and date match.
Selecting other bit combinations does not produce meaningful
results. However, the alarm circuit must follow the functions
described.
There are two ways a user can detect an alarm event. They are
by reading the AF flag or monitoring the INT pin. The AF flag in
the Flags register at 0x1FFF0 indicates that a date and time
match has occurred. The AF bit is set to ‘1’ when a match occurs.
Reading the Flags or Control register clears the Alarm flag bit
(and all others). A hardware interrupt pin is also used to detect
an alarm event.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator is running for the watchdog to function. It begins
counting down from the value loaded in the Watchdog Timer
register.
The counter consists of a loadable register and a free running
counter. On power up, the watchdog timeout value in register
0x1FFF7 is loaded into the counter load register. Counting
begins on power up and restarts from the loadable value any time
the watchdog strobe (WDS) bit is set to ‘1’. The counter is
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