CY23FS08
Document #: 38-07518 Rev. *C
Page 3 of 12
FailSafe Function
The CY23FS08 is targeted at clock distribution applications
that could or which currently require continued operation
should the main reference clock fail. Existing approaches to
this requirement have utilized multiple reference clocks with
either internal or external methods for switching between
references. The problem with this technique is that it leads to
interruptions (or glitches) when transitioning from one
reference to another, often requiring complex external circuitry
or software to maintain system stability. The technique imple-
mented in this design completely eliminates any switching of
references to the PLL, greatly simplifying system design.
The CY23FS08 PLL is driven by the crystal oscillator, which is
phase-aligned to an external reference clock so that the output
of the device is effectively phase-aligned to reference via the
external feedback loop. This is accomplished by utilizing a
digitally controlled capacitor array to pull the crystal frequency
over an approximate range of ±300 ppm from its nominal
frequency.
In this mode, should the reference frequency fail (i.e., stop or
disappear), the DCXO maintains its last setting and a flag
signal (FAIL#/SAFE) is set to indicate failure of the reference
clock.
The CY23FS08 provides four select bits, S1 through S4 to
control the reference to crystal frequency ratio. The DCXO is
internally tuned to the phase and frequency of the external
reference only when the reference frequency divided by this
ratio is within the DCXO capture range. If the frequency is out
of range, a flag will be set on the FAIL#/SAFE pin notifying the
system that the selected reference is not valid. If the reference
moves in range, then the flag will be cleared, indicating to the
system that the selected reference is valid.
Table 2. FailSafe Timing Table
Parameter
Description
Conditions
Min.
Max.
Unit
tFSL
Fail#/Safe Assert Delay
Measured at 80% to 20%, Load = 15 pF
See Figure 2
ns
tFSH
Fail#/Safe Deassert Delay
Measured at 80% to 20%, Load = 15 pF
See Figure 2
ns
RE F
OU T
FA I L # / S A FE
t
FS L
t
FS H
Figure 1. Fail#/Safe Timing for Input Reference Failing Catastrophically
n = F RE F
F
XT A L
=4 ( in abo v e ex am ple )
t
FS L ( m a x ) = 2
t
RE F x
n
(
)
+
25ns
t
FS H ( m in ) = 1 2
t
RE F x n
(
)
+
25 ns
Figure 2. Fail#/Safe Timing Formula
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