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CY14E064L
Document Number: 001-06543 Rev. *D
Page 2 of 17
Pin Configurations
Pin Definitions
Pin Name
IO Type
Description
A0–A12
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
DQ0-DQ7
Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, writes data on the IO pins to the address
location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply
Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a non-volatile STORE operation. A weak internal pull
up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply
AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
non-volatile elements.
VCAP
A12
A7
A6
A5
A4
VCC
HSB
WE
A8
A9
A11
OE
A10
DQ6
DQ7
DQ5
CE
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
DQ0
A3
A2
A1
A0
DQ1
DQ2
28-SOIC
Top View
(Not To Scale)
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