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CY23S08
Document #: 38-07265 Rev. *G
Page 3 of 10
Spread Aware
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been
one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant
amount of tracking skew which may cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with
Spread Spectrum Frequency Timing Generator (SSFTG) ICs.
Table 2. Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
0
Three-State
Three-State
PLL
Y
0
1
Driven
Three-State
PLL
N
1
0
Driven
Driven
Reference
Y
1
1
Driven
Driven
PLL
N
Table 3. Available CY23S08 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
CY23S08–1
Bank A or Bank B
Reference
Reference
CY23S08–1H
Bank A or Bank B
Reference
Reference
CY23S08–2
Bank A
Reference
Reference/2
CY23S08–2H
Bank A
Reference
Reference/2
CY23S08–2
Bank B
2 X Reference
Reference
CY23S08–2H
Bank B
2 X Reference
Reference
CY23S08–3
Bank A
2 X Reference
Reference or Reference[1]
CY23S08–3
Bank B
4 X Reference
2 X Reference
CY23S08–4
Bank A or Bank B
2 X Reference
2 X Reference
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