PRELIMINARY
CY28SRC04
Document #: 001-00043 Rev. *A
Page 2 of 10
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Pin Description
Pin No.
Name
Type
Description
12
IREF
I
A precision resistor attached to this pin is connected to the internal current
reference.
20
SCLK
I, PU
SMBus compatible SCLOCK. This pin has an internal pull-up.
21
SDATA
I/O, PU SMBus compatible SDATA.
This pin has an internal pull-up.
1, 2, 5, 6, 7, 8,
23, 24
SRCT/C[4:1]
O, DIF 100-MHz Differential Serial reference clock.
18
XIN
I
14.318-MHz Crystal Input
19
XOUT
O
14.318-MHz Crystal Output
4, 10, 22
VDD_SRC
PWR
3.3V power supply for SRC outputs
3, 9, 11
VSS_SRC
GND
Ground for SRC outputs
14
VDDA
PWR
3.3V Analog Power for PLLs
13
VSSA
GND
Analog Ground
17
VDD_REF
PWR
3.3V power supply for Xtal
16
VSS_REF
GND
Ground for Xtal
15
NC
NC
No Connect
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:5)
Chip select address, set to ‘00’ to access device
(4:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
8:2
Slave address – 7 bits
8:2
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count – 8 bits
20
Repeat start
28
Acknowledge from slave
27:21
Slave address – 7 bits
36:29
Data byte 1 – 8 bits
28
Read = 1
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