CY27EE16ZE
Document #: 38-07440 Rev. *C
Page 7 of 17
Power-down Mode (PDM) and Output Enable
(OE) Registers for Pin 10
In the default clock configuration, pin 10 is configured as OE,
and not configured as PDM. As such, the Power-down mode
is not available unless the clock core is modified.
To Configure for PDM
To configure pin 10 for PDM, use the SPI to write the following:
1. PDMEnable, Register 10H[2] = 1
2. PDMPadSel[1:0], Register 10H[1:0] =10
3. OESrc, Register 10H[7] = 1 (to redirect control of output
enable to memory, register 40H[7:6], and thereby enable
both divider banks).
Now, when the PDM signal (an active LOW signal) is asserted,
all of the clock components are shut down and the part enters
a low-power state.
The serial port and EE blocks will still be available. These
circuits automatically go into a low-power state when not being
used, but will draw power when active.
Note: For default factory programmed devices, Register
40H[7:6] may be programmed to 00. In this case Register
40H[7:6] must be programmed to 11 in order for clock outputs
to be enabled.
To Configure for OE
To reconfigure pin 10 as OE again, so that pin 10 controls
enable/disable of the output divider bank, use the SPI to write
the following:
1. OESrc, Register 10H[7] = 0
2. OE0PadSel[1:0], Register 10H[6:5] =10
3. OE1PadSel[1:0], Register 10H[4:3] =10
4. PDMEnable, Register 10H[2] = 0
5. Mem WP, Register 11H[4] = 0
6. WPSrc, Register 11H[3] = 1
Write Protect (WP) Registers
To reconfigure pin 17 as WP, to control enable/disable of write
protection, use the SPI to write the following:
WPSrc, Register 11H[3] = 0
WPPadSel[2:0], Register 11H[2:0] = 100
When active (WP = 1), WP prevents the control logic for the
EE from initiating a erase/program cycle for any of the
EEPROM blocks (16-Kbit scratchpad and clock configuration
block). All serial shifting works as normal.
PLL Frequency, Q Counter
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7 bit divider with a
maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2
is added to this register value to achieve the total Q, or Qtotal.
Qtotal is defined by the formula:
Qtotal = Q + 2.
The minimum value of Qtotal is 2. The maximum value of Qtotal
is 129. Register 42H is defined in Table 6.
Stable operation of the CY27EE16ZE cannot be guaranteed if
REF/Qtotal falls below 250 kHz. Qtotal bit locations and values
are defined in Table 6.
PLL Frequency, P Counter
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Qtotal) value to achieve the
VCO frequency. The product counter, defined as Ptotal, is
made up of two internal variables, PB and PO. The formula for
calculating Ptotal is:
Ptotal = (2(PB + 4) + PO)
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings (see section, "Charge Pump Settings
[40H(2..0)]", page 8”). The 3 MSBs of register 40H are preset
and reserved and cannot be changed.
PO is a single bit variable, defined in register 42H(7). This
allows for odd numbers in Ptotal.
The remaining 7 bits of 42H are used to define the Q counter,
as shown in Table 6.
The minimum value of Ptotal is 8. The maximum value of Ptotal
is 2055. To achieve the minimum value of Ptotal, PB and PO
should both be programmed to 0. To achieve the maximum
value of Ptotal, PB should be programmed to 1023, and PO
should be programmed to 1.
Stable operation of the CY27EE16ZE cannot be guaranteed if
the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below
100 MHz. Registers 40H, 41H and 42H are defined in Table 7.
Table 6. Q Counter Register Definition
Register
D7
D6
D5
D4
D3
D2
D1
D0
42H
PO
Q(6)
Q(5)
Q(4)
Q(3)
Q(2)
Q(1)
Q(0)
Table 7. P Counter Register Definition
Address
D7D6D5D4D3D2D1D0
40H
1
1
0
Pump(2)
Pump(1)
Pump(0)
PB(9)
PB(8)
41H
PB(7)
PB(6)
PB(5)
PB(4)
PB(3)
PB(2)
PB(1)
PB(0)
42H
PO
Q(6)
Q(5)
Q(4)
Q(3)
Q(2)
Q(1)
Q(0)
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