CY244/45ZXC
Document #: 38-07748 Rev. **
Page 2 of 9
General Description
The CY24xZXC family of devices has an Analog VCXO
(Voltage Controlled Crystal Oscillator), 4 PLLs, up to 7 clock
outputs, and frequency selection capabilities. The frequency
selects do not modify any PLL frequency. Instead, they allow
the user to choose between up to 8 different output divider
selections depending on the clock and package configuration.
This is illustrated in Frequency Selection tables 1 and 2.
There is one programmable OE/PDWN. The OE/PDWN pin
can be programmed as either an output enable pin or a power
down pin. The OE function can be programmed to disable a
selected set of outputs when low, leaving the remaining
outputs running. Full chip power-down will disable all outputs
as well as the PLLs and most of the active circuitry when low.
Factory-Programmable CY24xZXC
Factory programming is available for high or low volume
manufacturing by Cypress. All requests must be submitted to
the local Cypress Field Application Engineer (FAE) or sales
representative. Once the request has been processed, you will
receive a new part number, samples, and data sheet with the
programmed values. This part number will be used for
additional sample requests and production orders. Please
refer to the CY223388/89/91 data sheet for up to 8 clock
outputs and compatibility with most SMD type crystals.
PLLs
The advantage of having 4 PLLs is that a single device can
generate up to 4 independent frequencies from a single
crystal. Generally a design may require up to 4 oscillators to
accomplish what could be done with a single CY24xZXC.
Each PLL is independent and can be configured to generate
a VCO (Voltage Controlled Oscillator) frequency between
62.5 MHz and 250 MHz. Each PLL can then in turn be divided
down with post dividers to generate the clock output frequency
of the user’s choice. The output divider allows each clock
output to be divided by 1,2,3,4,6,8,9,10,12,15. The PLL
maximum is reduced to 166 MHz in divide by 1 mode due to
output buffer limitations.
Outputs that allow frequency switching perform the transition
free of glitches. A glitch is defined as a high or low time shorter
than half the smaller of the two periods being switched
between. Extended low time (even many cycles in duration) is
acceptable. Please refer to Figure 5.
In order to minimize PPM (Parts Per Million) error on the clock
outputs, a user should try and choose a crystal reference
frequency that is a common multiple of the desired PLL
frequencies. While this would be the ideal situation, this is not
always the case and the PLLs have high resolution counters
internally to help minimize frequency deviation from the
desired frequency.
PLL VCO frequencies are generated by the following
equation: FVCO = FREF * (P / Q)
Where FREF is the reference input frequency, P is the PLL
feedback divider and Q is the reference input divider. A PLL is
a feedback system where the VCO frequency divided by P and
reference frequency divided by Q are constantly being
compared and the VCO frequency is adjusted to achieve a
locked state. Figure 1 is a simplified drawing of a PLL.
Note:
1. Pin 5 16-pin TSSOP (choice between clock output or OE/PD)
Pin Description
Pin Name
Pin Number
Pin Description
16-pin TSSOP
20-pin TSSOP
XIN
1
1
Crystal Input or Reference Clock Input
XOUT
16
20
Crystal Output (No connect if external clock is used)
CLKA
5[1]
7
Clock Output
CLKB
7
9
Clock Output
CLKC
9
11
Clock Output
CLKD
N/A
14
Clock Output
CLKE
N/A
15
Clock Output
CLKF
13
17
Clock Output
CLKG
14
18
Clock Output
FS0
10
12
Frequency Select 0
FS1
8
10
Frequency Select 1
FS2
N/A
2
Frequency Select 2
OE/PD
5[1]
6
Output Enable Control/Power Down
VIN
3
4
Analog Control Input for VCXO
VDD
11,15
13,19
Voltage Supply
VSS
6,12
8,16
Ground
AVDD
2
3
Analog Voltage Supply
AVSS
4
5
Analog Ground
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