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CY2077
Document Number: 38-07210 Rev. *C
Page 8 of 14
Switching Waveforms
Figure 2. Duty Cycle Timing (t1w, t1x, t1y)
Figure 3. Output Rise/Fall Time
Figure 4. Power down Timing (synchronous and asynchronous modes)
Figure 5. Power up Timing
Figure 6. Output Enable Timing (synchronous and asynchronous modes)
Notes
6. In synchronous mode, the power down or output three-state is not initiated until the next falling edge of the output clock.
7. In asynchronous mode, the power down or output three-state occurs within 25 ns regardless of position in the output clock cycle.
t1A
t1B
OUTPUT
OUTPUT
t2
VDD
0V
t3
CLKOUT
VDD
t4
1/f
t5a
VIL
VIH
POWER
DOWN
0V
1/f
t5b
CLKOUT
T
(synchronous
[6])
(asynchronous
[7])
CLKOUT
VDD
t6
1/f
VDD – 10%
POWER
UP
0V
min 30 μs
max 30 ms
CLKOUT
VDD
OUTPUT
ENABLE
0V
VIL
t7a
t8
High Impedance
CLKOUT
t7b
t8
High Impedance
T
(synchronous
[6])
(asynchronous
[7])
VIH
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