CY2305
CY2309
Document #: 38-07140 Rev. *G
Page 2 of 14
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Pin Description for CY2309
Pin
Signal
Description
1REF[1]
Input reference frequency, 5V-tolerant input
2
CLKA1[2]
Buffered clock output, Bank A
3
CLKA2[2]
Buffered clock output, Bank A
4VDD
3.3V supply
5
GND
Ground
6
CLKB1[2]
Buffered clock output, Bank B
7
CLKB2[2]
Buffered clock output, Bank B
8S2[3]
Select input, bit 2
9S1[3]
Select input, bit 1
10
CLKB3[2]
Buffered clock output, Bank B
11
CLKB4[2]
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[2]
Buffered clock output, Bank A
15
CLKA4[2]
Buffered clock output, Bank A
16
CLKOUT[2]
Buffered output, internal feedback on this pin
Pin Description for CY2305
Pin
Signal
Description
1REF[1]
Input reference frequency, 5V-tolerant input
2CLK2[2]
Buffered clock output
3CLK1[2]
Buffered clock output
4
GND
Ground
5CLK3[2]
Buffered clock output
6VDD
3.3V supply
7CLK4[2]
Buffered clock output
8
CLKOUT[2]
Buffered clock output, internal feedback on this pin
Select Input Decoding for CY2309
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT[4]
Output Source
PLL Shutdown
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
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