CY2304
Document #: 38-07247 Rev. *D
Page 2 of 8
Zero Delay and Skew Control
To close the feedback loop of the CY2304, the FBK pin can be
driven from any of the four available output pins. The output
driving the FBK pin will be driving a total load of 7 pF plus any
additional load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the
input-output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally
loaded. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the
feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
For further information on using CY2304, refer to the appli-
cation note “CY2308: Zero Delay Buffer.”
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
Pin Description
Pin
Signal
Description
1REF[1]
Input reference frequency, 5V-tolerant input
2
CLKA1[2]
Clock output, Bank A
3
CLKA2[2]
Clock output, Bank A
4
GND
Ground
5
CLKB1[2]
Clock output, Bank B
6
CLKB2[2]
Clock output, Bank B
7VDD
3.3V supply
8
FBK
PLL feedback input
REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
