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CY2305SXI-1 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY2305SXI-1
Description  Low-Cost 3.3V Zero Delay Buffer
Download  14 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2305SXI-1 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY2305
CY2309
Document #: 38-07140 Rev. *G
Page 6 of 14
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices [7]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
t1
Output Frequency
30-pF load
10-pF load
10
10
–100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
t3
Rise Time[6]
Measured between 0.8V and 2.0V
2.50
ns
t4
Fall Time[6]
Measured between 0.8V and 2.0V
2.50
ns
t5
Output to Output Skew[6]
All outputs equally loaded
85
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
15
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT
pins of devices
––
700
ps
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67 MHz, loaded
outputs
–70
200
ps
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
––
1.0
ms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices[7]
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Frequency
30-pF load
10-pF load
10
10
100
133.33
MHz
MHz
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout < 50.0 MHz
45.0
50.0
55.0
%
t3
Rise Time[6]
Measured between 0.8V and 2.0V
1.50
ns
t4
Fall Time[6]
Measured between 0.8V and 2.0V
1.50
ns
t5
Output to Output Skew[6]
All outputs equally loaded
85
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
15
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT
pins of devices
700
ps
t8
Output Slew Rate[6]
Measured between 0.8V and 2.0V
using Test Circuit #2
1–
V/ns
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67 MHz, loaded
outputs
60
200
ps
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
––
1.0
ms


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