PRELIMINARY
1 PLL In-System Programmable Clock Generator
CY22701
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07698 Rev. *B
Revised February 8, 2005
Features
• In-system programmable through I2C Serial
Programming Interface (SPI)
• Programmable SRAM and non-volatile EEPROM
memory bits with 3.3V supply
• Integrated, phase-locked loop with programmable P
and Q counters, output dividers
• Low-jitter, high-accuracy outputs
• 3.3V Operation
•8-lead SOIC
Benefits
• Custom timing solutions for designs not suitable for
factory custom silicon, Xtals, or ASICs for production
• Program and optimize designs while chip is on system
board
• Programming voltages contained in chip
• High-performance PLL enables control of output
frequencies that are customizable to support a wide
range of applications
• Meets critical timing requirements in complex system
designs
• Meets industry-standard voltage platforms
• Industry standard packaging saves on board space
Part Number
No. of Outputs
Input Frequency Range
Output Frequency Range
CY22701
2
1 – 167 MHz (Driven Clock Input) {Commercial}
1 –150 MHz (Driven Clock Input) {Industrial}
8 – 30 MHz (Crystal Reference) {Comm. or Ind.}
80 kHz – 200 MHz (3.3V) {Commercial}
80 kHz –167 MHz (3.3V) {Industrial}
Logic Block Diagram
XIN
XOUT
CLK2
OUTPUT
DIVIDERS
PLL
OSC
CLK1
Q
VCO
VDD VSS
Φ
P
Pin Configuration
SCL
SDAT
EEPROM
Memory Array
Clock
Configuration
Output
Crosspoint
Switch
Array
[I2C- SPI:]
WP
XOUT
CLK2/WP
CLK1
SCL
8 PIN SOIC
8
7
6
5
1
2
3
4
XIN
VDD
SDA
VSS