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PRELIMINARY
MediaClock™
MPEG Clock Generator with VCXO
CY24212
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07402 Rev. *C
Revised April 6, 2005
Features
Benefits
• Integrated phase-locked loop (PLL)
Highest-performance PLL tailored for multimedia applications
• Low jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
• VCXO with analog adjust
Large ±150-ppm range, better linearity
• 3.3V operation
Enables application compatibility
Part Number Outputs
Input Frequency Range
Output Frequencies
CY24212-1
1
13.5 MHz/27 MHz (selectable)
27 MHz
CY24212-2
2
13.5 MHz/27 MHz (selectable)
Two copies of 27 MHz
CY24212-3
2
27 MHz
27 MHz/27.027 MHz (-1 ppm)
CY24212-5
2
27 MHz
27 MHz/27.027 MHz (0 ppm)
Logic Block Diagram
XOUT
OUTPUT
DIVIDERS
PLL
OSC
VCXO
Q
P
VCO
VDD
VSS
Φ
CLKA (27 MHz)
XIN
FSEL
27 MHz (-2)
27/27.027 MHz (-3)
8-pin SOIC
CY24212-1
Pin Configurations
1
2
3
4
XOUT
XIN
VCXO
CLKA 27 MHz
VSS
VSS
FSEL
5
6
7
8
VDD
8-pin SOIC
CY24212-2
1
2
3
4
XOUT
XIN
VCXO
CLKA 27 MHz
VSS
CLKB 27 MHz
FSEL
5
6
7
8
VDD
8-pin SOIC
CY24212-3,-5
1
2
3
4
XOUT
XIN
VCXO
CLKA 27 MHz
VSS
CLKB (27/27.027 MHz)
FSEL
5
6
7
8
VDD
Table 1. CY24212 (-1, -2) Frequency Select Option
FSEL
Reference
CLKA/CLKB
0
13.5 MHz
27 MHz
1
27 MHz
27 MHz
Table 2. CY24212 (-3, -5) Frequency Select Option
FSEL
Reference
CLKA
CLKB
0
27 MHz
27 MHz
27 MHz
1
27 MHz
27 MHz
27.027 MHz
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