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PRELIMINARY
CY24212
Document #: 38-07402 Rev. *C
Page 3 of 6
DC Electrical Specifications
Parameter
Name
Description
Min
Typ
Max
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD = 3.3V (source)
12
24
mA
IOL
Output Low Current
VOL = 0.5, VDD = 3.3V (sink)
12
24
mA
CIN
Input Capacitance
7pF
IIH
Input High Current
VIH = VDD
–5
10
µA
IIL
Input Low Current
VIL = 0V
–
–
50
µA
f∆XO
VCXO Pullability Range
±150
ppm
VVCXO
VCXO Input Range
0
VDD
V
IDD
Supply Current
Sum of Core and Output Current
35
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0.3
VDD
RUP
Pull-up resistor on inputs
VDD = 3.14 to 3.47V, measured VIN = 0V
100
150
k
Ω
AC Electrical Specifications (VDD = 3.3V)
Parameter[3]
Name
Description
Min
Typ
Max
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
55
%
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20%
to 80% of VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
t9
Clock Jitter
Peak-to-peak period jitter
300
ps
t10
PLL Lock Time
3ms
Test and Measurement Set-up
Note:
3. Not 100% tested.
0.1
µF
VDDs
Outputs
CLOAD
GND
DUT
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