CY28324_02 datasheet(6/23 Pages) CYPRESS | FTG for Intel® Pentium® 4 CPU and Chipsets

6 page

PRELIMINARY

CY28324

Document #: 38-07002 Rev. *B

Page 6 of 23

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions such as individual

clock output buffers, etc., can be individually enabled or dis-

abled.

The registers associated with the Serial Data Interface initial-

izes to their default setting upon power-up, and therefore use

of this interface is optional. Clock device register changes are

normally made upon system initialization, if any are required.

The interface can also be used during system operation for

power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operation from the controller. For

block write/read operation, the bytes must be accessed in se-

quential order from lowest to highest byte (most significant bit

first) with the ability to stop after any complete byte has been

transferred. For byte write and byte read operations, the sys-

tem controller can access individual indexed bytes. The offset

of the indexed byte is encoded in the command code, as de-

scribed in Table 1.

The block write and block read protocol is outlined in Table 2

while Table 2 outlines the corresponding byte write and byte

read protocol.

The slave receiver address is 11010010 (D2h).

Table 1. Command Code Definition

Bit

Descriptions

0 = Block read or block write operation

1 = Byte read or byte write operation

6:0

Byte offset for byte read or byte write operation. For block read or block write operations, these

bits should be ‘0000000’.

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

1Start

2:8

Slave address – 7 bits

2:8

Slave address – 7 bits

9Write

Acknowledge from slave

11:18

Command Code – 8 bits

‘00000000’ stands for block operation

11:18

Command Code – 8 bits

‘00000000’ stands for block operation

Acknowledge from slave

20:27

Byte Count – 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address – 7 bits

29:36

Data byte 0 – 8 bits

Read

Acknowledge from slave

38:45

Data byte 1 – 8 bits

30:37

Byte count from slave – 8 bits

Acknowledge from slave

Acknowledge

...

Data Byte N/Slave Acknowledge...

39:46

Data byte from slave – 8 bits

...

Data Byte N – 8 bits

Acknowledge

...

Acknowledge from slave

48:55

Data byte from slave – 8 bits

...

Stop

Acknowledge

...

Data bytes from slave/Acknowledge

...

Data byte N from slave – 8 bits

...

Not acknowledge

...

Stop

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