PRELIMINARY
CY28324
Document #: 38-07002 Rev. *B
Page 3 of 23
PCI_F2/Mode
8
I/O
Free-running PCI Output 2/Mode Selection: 3.3V free-running PCI output.
This pin also serves as a power-on strap option to determine the functions of
3VMREF/CPU_STP# and 3VMREF#/PCI_STP#.
When Mode input is sampled HIGH during power-on reset,
3VMREF/CPU_STP# and 3VMREF#/PCI_STP# will be configured as
3VMREF and 3VMREF# output, respectively.
When Mode input is sampled LOW during power-on reset,
3VMREF/CPU_STP# and 3VMREF#/PCI_STP# will be configured as
CPU_STP# and PCI_STP# input, respectively.
PCI0/FS4
10
I/O
PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also serves as
a power-on strap option to determine device operating frequency as described
in the Frequency Selection Table.
PCI1:6
11, 12, 14, 15,
16, 17
O
PCI Clock Output 1 to 6: 3.3V PCI clock outputs.
48MHz/FS0
22
I/O
48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread spec-
trum output. This pin also serves as a power-on strap option to determine
device operating frequency as described in Table 4.
This output will be used as the reference clock for USB host controller in Intel
845 (Brookdale) platforms. For Intel Brookdale - G platforms, this output will
be used as the VCH reference clock.
24_48MHz/FS1
23
I/O
24- or 48-MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or 48-MHz
non-spread spectrum output. This pin also serves as a power-on strap option
to determine device operating frequency as described in Table 4.
This output will be used as the reference clock for SIO devices in Intel 845
(Brookdale) platforms. For Intel Brookdale - G platforms, this output will be
used as the reference clock for both USB host controller and SIO devices. We
recommend system designer to configure this output as 48 MHz and “HIGH
Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively.
PWR_DWN#
42
I
Power Down Control: 3.3V LVTTL-compatible input that places the device in
power down mode when held LOW.
SCLK
26
I
SMBus Clock Input: Clock pin for serial interface.
SDATA
25
I/O
SMBus Data Input: Data pin for serial interface.
RST#
20
O
(open-
drain)
System Reset Output: Open-drain system reset output.
IREF
35
I
Current Reference for CPU Output: A precision resistor is attached to this
pin, which is connected to the internal current reference.
VTT_PWRGD#
19
I
Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL input.
VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4,
MODE and MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW).
Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
VDD_MREF
2, 9, 18, 24,
32, 39, 46
P
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output
buffers, PCI output buffers, reference output buffers and 48-MHz output buffers.
Connect to 3.3V.
Pin Definitions(continued)
Pin Name
Pin No.
Pin
Type
Pin Description
