CY28341-3 datasheet(6/19 Pages) CYPRESS

Part #	CY28341-3

Description	Universal Clock Chip for VIA?줡4M/KT/KM400A DDR Systems

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Manufacturer	CYPRESS [Cypress Semiconductor]

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PRELIMINARY

CY28341-3

Document #: 38-07580 Rev. **

Page 6 of 19

2

1

14

PCI3

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

1

12

PCI2

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

0

1

11

PCI1

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

Byte 3: AGP/Peripheral Clocks Register

Bit

@Pup

Pin#

Name

Description

70

21

24_48M

0 = pin21 output is 24MHz. Writing a '1' into this register asynchronously

changes the frequency at pin21 to 48 MHz.

6

1

20

48MHz

1 = output enabled (running). 0 = output disabled asynchronously in a low

5

1

21

24_48M

1 = output enabled (running). 0 = output disabled asynchronously in a low

4

0

6,7,8

DASAG1

Programming these bits allow shifting skew of the AGP(0:2) signals

relative to their default value. See Table 5.

3

0

6,7,8

DASAG0

2

1

8

AGP2

1 = output enabled (running). 0 = output disabled asynchronously in a low

1

7

AGP1

1 = output enabled (running). 0 = output disabled asynchronously in a low

0

1

6

AGP0

1 = output enabled (running). 0 = output disabled asynchronously in a low

Byte 2: PCI Clock Register (continued)

Table 5. Dial-a-Skew

 AGP(0:2)

DASAG (1:0)

AGP(0:2) Skew Shift

00

Default

01

–280 ps

10

+280 ps

11

+480 ps

Byte 4: Peripheral Clocks Register

Bit

@Pup

Pin#

Name

Description

7

1

20

48M

1 = Low strength, 0 = High strength

6

1

21

24_48M

1 = Low strength, 0 = High strength

5

0

6,7,8

DARAG1

Programming these bits allow modifying the frequency ratio of the

AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See Table 6.

4

0

6,7,8

DARAG0

3

1

REF0

1 = output enabled (running). 0 = output disabled asynchronously in a low

2

1

56

REF1

1 = output enabled (running). 0 = output disabled asynchronously in a low

1

REF0

1 = Low strength, 0 = High strength

0

1

56

REF1

1 = Low strength, 0 = High strength (K7 Mode only)

Table 6. Dial-A-Ratio

 AGP(0:2)

DARAG (1:0)

CU/AGP Ratio

00

Frequency Selection Default

01

2/1

10

2.5/1

11

3/1

Byte 5: SDR/DDR Clock Register

Bit

@Pup

Pin#

Name

Description

70

45

BUF_IN

threshold

voltage

DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V

6

1

46

FBOUT

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

5

1

29,30

DDRT/C5

1 = output enabled (running). 0 = output disabled asynchronously in a low state.

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