CY28346
Document #: 38-07331 Rev. *C
Page 8 of 20
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 5.
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown in Figure 6.
The Tpd is the prop delay from the input pin (66IN) to the
output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The
measurement taken at 1.5V.
66B(0:2) to PCI Buffered Clock Skew
Figure 7 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
Figure 8 shows the timing relationship between 3V66(0:5) and
PCI(0:6) and PCI_F(0:2) when configured to run in the unbuf-
fered mode.
Ro
3000
Ω (recommended)
N/A
Ros
Vout
N/A
1.2V
Table 4. Host Clock (HCSL) Buffer Characteristics
Table 5. CPU Clock Current Select Function
Mult0
Board Target Trace/Term Z
Reference R, Iref – Vdd (3*Rr)
Output Current
Voh @ Z
050
Ω
Rr = 221 1%, Iref = 5.00mA
Ioh = 4*Iref
1.0V @ 50
150
Ω
Rr = 475 1%, Iref = 2.32mA
Ioh = 6*Iref
0.7V @ 50
Table 6. Group Timing Relationship and Tolerances
Description
Offset
Tolerance
Conditions
3V66 to PCI
2.5 ns
±1.0 ns
3V66 Leads PCI (unbuffered mode)
48MUSB to 48MDOT Skew
0.0 ns
±1.0 ns
0 degrees phase shift
66B(0:2) to PCI offset
2.5 ns
±1.0 ns
66B Leads PCI (buffered mode)
48MUSB
48MDOT
Figure 5. 48MUSB and 48MDOT Phase Relationship
66IN
66B(0:2)
Tpd
Figure 6. 66IN to 66B(0:2) Output Delay Figure
66B(0:2)
PCI(0:6)
PCIF(0:2)
1.5-
3.5ns
Figure 7. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
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