CY28341-2
Document #: 38-07471 Rev. *D
Page 2 of 19
Pin Description[2]
Pin Number
Pin Name
PWR
I/O
Pin Description
3XIN
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
4
XOUT
VDD
O Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
1
FS0/REF0
VDDR
I/O
PU
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
the power supply voltage crosses the input threshold voltage, FS0 state is
latched and this pin becomes REF0, buffered copy of signal applied at XIN.
(1-2 x strength, selectable by SMBus. Default value is 1 x strength.)
56
VTTPWRGD#
VDDR
I
If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At power-up,
VTT_PWRGD# is an input. When this input transitions to a logic low, the FS
(3:0) and MULTSEL are latched and all output clocks are enabled. After the
first high to low transition on VTT_PWRGD#, this pin is ignored and will not
effect the behavior of the device thereafter. When the VTT_PWRGD# feature
is not used, please connect this signal to ground through a 10K
Ω resistor.
REF1
VDDR
O If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin
becomes REF1 and is a buffered copy of the signal applied at XIN.
44,42,38,
36,32,30
DDRT
(0:5)/SDRAM
(0,2,4,6,8,10)
VDDD
O These pins are programmable through strapping pin11, SELSDR_DDR#.
If SELSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They
are “True” copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must
be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase
with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V
43,41,37
35,31,29
DDRC
(0:5)/SDRAM
(1,3,5,7,9,11)
VDDD
O These pins are programmable through strapping pin11, SELSDR_DDR#.
If SelSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They
are “Complementary” copies of signal applied at Pin45, BUF_IN. In this mode,
VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(1,3,5,7,9,11) single ended clock outputs, copies of (and in phase
with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V.
7
SELP4_K7 /
AGP1
VDDAGP I/O
PU
Power-on Bidirectional Input/Output. At power-up, SELP4_K7 is the input.
When the power supply voltage crosses the input threshold voltage,
SELP4_K7 state is latched and this pin becomes AGP1 clock output.
SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode.
12
MULTSEL/PCI2
VDDPCI I/O
PU
Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input.
When the power supply voltage crosses the input threshold voltage,
MULTSEL state is latched and this pin becomes PCI2 clock output. MULTSEL
= 0, Ioh is 4 x IREFMULTSEL = 1, Ioh is 6 x IREF
53
CPUT/CPUOD_T
VDDC
O 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock
Output. See Table 1
52
CPUC/CPUOD_C
VDDC
O 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock
Output. See Table 1
48,49
CPUCS_T/C
VDDI
O 2.5V CPU Clock Outputs for Chipset. See Table 1.
14,15,17,18 PCI (3:6)
VDDPCI
O PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1
10
FS1/PCI_F
VDDPCI I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
the power supply voltage crosses the input threshold voltage, FS1 state is
latched and this pin becomes PCI_F clock output.
20
FS3/48M
VDD48M I/O
PD
Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When
the power supply voltage crosses the input threshold voltage, FS3 state is
latched and this pin becomes 48M, a USB clock output.
Note:
2. PU = internal pull-up. PD = internal pull-down. Typically = 250 k
Ω (range 200 kΩ to 500 kΩ).
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