PRELIMINARY
CY28346-2
Document #: 38-07509 Rev. *B
Page 5 of 20
Byte 3: PCIF Clock and 48M Control Register (all bits are read and write functional)
Bit
@Pup
Name
Description
7
1
48M_DOT
48M_DOT Output Control,1 = enabled, 0 = forced LOW
6
1
48M_USB
48M_USB Output Control,1 = enabled, 0 = forced LOW
5
0
PCIF2
PCI_STP#, control of PCIF2.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
4
0
PCIF1
PCI_STP#, control of PCIF1.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
3
0
PCIF0
PCI_STP#, control of PCIF0.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
2
1
PCIF2
PCIF2 Output Control. 1=running, 0=forced LOW
1
1
PCIF1
PCIF1 Output Control. 1= running, 0=forced LOW
0
1
PCIF0
PCIF0 Output Control. 1= running, 0=forced LOW
Byte 4: DRCG Control Register(all bits are read and write functional)
Bit
@Pup
Name
Description
7
0
SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread)
60
Reserved
5
1
3V66_0
3V66_0 Output Enabled. 1 = enabled, 0 = disabled
4
1
3V66_1/VCH
3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled
3
1
3V66_5
3V66_5 Output Enable. 1 = enabled, 0 = disabled
2
1
66B2/3V66_4
66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled
1
1
66B1/3V66_3
66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled
0
1
66B0/3V66_2
66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled
Byte 5: Clock Control Register (all bits are read and write functional)
Bit
@Pup
Name
Description
7
0
SS1 Spread Spectrum control bit
6
1
SS0 Spread Spectrum control bit
5
0
66IN to 66M delay Control MSB
4
0
66IN to 66M delay Control LSB
30
Reserved
2
0
48M_DOT edge rate control. When set to 1, the edge is slowed by 15%.
10
Reserved
0
0
USB edge rate control. When set to 1, the edge is slowed by 15%
Byte 6: Silicon Signature Register[2] (all bits are read-only)
Bit
@Pup
Name
Description
70
60
50
41
3
0
Vendor Code, 011 = IMI
20
11
01
Note:
2. When writing to this register the device will acknowledge the write operation, but the data itself will be ignored.
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