CY28352
Document #: 38-07371 Rev. *C
Page 4 of 8
Maximum Ratings[3]
Input Voltage Relative to VSS:.............................. VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD:............ VDD + 0.3V
Storage Temperature: ................................ –65
°C to + 150°C
Operating Temperature: .................................... 0
°C to +70°C
Maximum Power Supply: ................................................3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDDA = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C
[4]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
SDATA, SCLK
1.0
V
VIH
Input High Voltage
SDATA, SCLK
2.2
V
VIL
Input Voltage Low
CLKIN, FBIN
0.4
V
VIH
Input Voltage High
CLKIN, FBIN
2.1
V
IIN
Input Current
VIN = 0V or VIN = VDDQ, CLKIN,
FBIN
–10
10
µA
IOL
Output Low Current
VDDQ = 2.375V, VOUT = 1.2V
26
35
mA
IOH
Output High Current
VDDQ = 2.375V, VOUT = 1V
–18
–32
mA
VOL
Output Low Voltage
VDDQ = 2.375V, IOL = 12 mA
0.6
V
VOH
Output High Voltage
VDDQ = 2.375V, IOH = –12 mA
1.7
V
VOUT
Output Voltage Swing[5]
1.1
VDDQ – 0.4
V
VOC
Output Crossing Voltage[6]
(VDDQ/2) – 0.2
VDDQ/2
(VDDQ/2) + 0.2
V
IOZ
High-Impedance Output
Current
VO = GND or VO = VDDQ
–10
10
µA
IDDQ
Dynamic Supply Current[7]
All VDDQ and VDDI,
FO = 170 MHz
235
300
mA
IDSTAT
Static Supply Current
1mA
IDD
PLL Supply Current
VDDA only
9
12
mA
Cin
Input Pin Capacitance
4
6
pF
AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C
[7, 9]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fCLK
Operating Clock Frequency
60
200
MHz
tDC
Input Clock Duty Cycle
40
60
%
tlock
Maximum PLL lock Time
100
µs
Tr / Tf
Output Clocks Slew Rate
20% to 80% of VOD
1
2.5
V/ns
tpZL, tpZH
Output Enable Time[10]
(all outputs)
3ns
tpLZ, tpHZ
Output Disable Time[10]
(all outputs)
3ns
tCCJ
Cycle-to-Cycle Jitter[12]
f > 66 MHz
–100
100
ps
tjit(h-per)
Half-period jitter[12]
f > 66 MHz
–100
100
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. For load conditions, see Figure 7.
6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7.
7. All outputs switching loaded with 16 pF in 60
Ω environment. SeeFigure 7.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz, with a down
spread of –0.5%.
10. Refers to transition of non-inverting output.
11. All differential input and output terminals are terminated with 120
Ω/16 pF as shown in Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate, and must be met independently of each other.