PRELIMINARY
CY28439
Document #: 38-07668 Rev. *D
Page 9 of 22
Byte 12: Control Register 12
Bit
@Pup
Name
Description
7
0
CPU_DAF_N8
If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the FSEL[3:0] register will be used.
6
0
CPU_DAF_M6
5
0
CPU_DAF_M5
4
0
CPU_DAF_M4
3
0
CPU_DAF_M3
2
0
CPU_DAF_M2
1
0
CPU_DAF_M1
0
0
CPU_DAF_M0
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
0
SRC_N7
SRC Dial-A-Frequency Bit N7
6
0
SRC_N6
SRC Dial-A-Frequency Bit N6
5
0
SRC_N5
SRC Dial-A-Frequency Bit N5
4
0
SRC_N4
SRC Dial-A-Frequency Bit N4
3
0
SRC_N3
SRC Dial-A-Frequency Bit N3
2
0
SRC_N2
SRC Dial-A-Frequency Bit N2
1
0
SRC_N1
SRC Dial-A-Frequency Bit N1
0
0
SRC_N0
SRC Dial-A-Frequency Bit N0
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
0
SRC_N8
SRC Dial-A-Frequency Bit N8
6
0
SW_RESET
Software Reset.
When set the device will assert a reset signal on SRESET# upon
completion of the block/word/byte write that set it. After asserting and
deasserting the SRESET# this bit will self clear (set to 0).
The SRESET# pin must be enabled by latching SRESET#_EN on
VTT_PRWGD# to utilize this feature.
5
0
FS_[E:A]
FS_Override
0 = Select operating frequency by FS(E:A) input pins
1 = Select operating frequency by FSEL_(4:0) settings
4
0
SMSW_SEL
Smooth switch select
0: Select CPU_PLL
1: Select SRC_PLL.
3
0
RESERVED
RESERVED, Set = 0
2
0
RESERVED
RESERVED, Set = 0
1
1
PCIF
Free running 33-MHz Output Drive Strength
0 = 2x, 1 = 1x
0
0
Recovery_N8
Watchdog Recovery Bit
Byte 15: Control Register 15
Bit
@Pup
Name
Description
7
0
Recovery N7
Watchdog Recovery Bit
6
0
Recovery N6
Watchdog Recovery Bit
5
0
Recovery N5
Watchdog Recovery Bit
4
0
Recovery N4
Watchdog Recovery Bit
3
0
Recovery N3
Watchdog Recovery Bit
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