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AVR32UC Datasheet(PDF) 7 Page - ATMEL Corporation

Part # AVR32UC
Description  Technical Reference Manual
Download  118 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AVR32UC Datasheet(HTML) 7 Page - ATMEL Corporation

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7
32002C–AVR32–11/07
AVR32
Figure 2-2.
The Status Register high halfword
Figure 2-3.
The Status Register low halfword
DM - Debug State Mask
If this bit is set, the Debug State is masked and cannot be entered. The bit is cleared at reset,
and can both be read and written by software.
D - Debug State
The processor is in debug state when this bit is set. The bit is cleared at reset and should only be
modified by debug hardware, the breakpoint instruction or the retd instruction. Undefined behav-
iour may result if the user tries to modify this bit using other mechanisms.
M2, M1, M0 - Execution Mode
These bits show the active execution mode. The settings for the different modes are shown in
Table 2-1 on page 8. M2 and M1 are cleared by reset while M0 is set so that the processor is in
supervisor mode after reset. These bits are modified by hardware when initiating interrupt or
exception processing. Execution of the scall, rets or rete instructions will also change these bits.
Undefined behaviour may result if the user tries to modify these bits using the mtsr, ssrf or csrf
instructions. If software needs to change these bits, scall, rets or rete should be used, possibly
with prior modifications of the stack, to achieve the desired changes in a safe way. Refer to the
AVR32 Architecture Manual for the behaviour of these instructions, note especially how the
stack is modified after their execution.
Bit 31
0
0
0
Bit 16
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 3 Mask
Interrupt Level 2 Mask
1
0
0
0
0
1
1
0
0
0
0
0
0
FE
I0M
GM
M1
-
D
M0
EM
I2M
DM
-
M2
LC
1
-
Initial value
Bit name
I1M
Mode Bit 0
Mode Bit 1
-
Mode Bit 2
Reserved
Debug State
-
I3M
Reserved
Exception Mask
Global Interrupt Mask
Debug State Mask
Bit 15
Bit 0
Reserved
Carry
Zero
Sign
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
T
-
Bit name
Initial value
0
0
L
Q
V
N
Z
C
-
Overflow
Saturation
-
-
-
Lock
Reserved
Scratch


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