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PRELIMINARY
CY28443
Document #: 38-07716 Rev *C
Page 10 of 25
Byte 11: Control Register 11
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED Set = 0
6
HW
RESERVED
RESERVED
5
HW
RESERVED
RESERVED
4
HW
RESERVED
RESERVED
3
0
27MHz
27-MHz (spread and non-spread) Output Drive Strength
0 = Low, 1 = High
2
0
RESERVED
RESERVED Set = 0
1
0
RESERVED
RESERVED Set = 0
0
HW
RESERVED
RESERVED
Byte 12: Control Register 12
Bit
@Pup
Name
Description
7
0
CLKREQ#A
CLKREQ#A Enable
0 = Disable 1 = Enable
6
0
CLKREQ#B
CLKREQ#B Enable
0 = Disable 1 = Enable
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
1
96/100M Clock Speed
96/100 SRC Clock Speed
0 = 96 MHz, 1 = 100 MHz
5
1
RESERVED
RESERVED, Set = 1
4
1
RESERVED
RESERVED, Set = 1
3
1
PCI5
PCI5 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
2
1
PCI4
PCI4 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
1
1
PCI3
PCI3 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
0
1
PCI2
PCI2 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
1
RESERVED
RESEREVD
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
CLKREQ#A
SRC[T/C]5 Control
0 = SRC[T/C]5 not stoppable by CLKREQ#A
1 = SRC[T/C]5 stoppable by CLKREQ#A
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