PRELIMINARY
CY28443
Document #: 38-07716 Rev *C
Page 3 of 25
.
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot
functionality
in
that
once
a
valid
low
on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode
52
REF1/FCTSEL0
I/O, SE
PD
Fixed 14.318-MHz Clock Output / 3.3 LVTTL input for selecting for pin 14,
15 (DOT96[T/C], 27M-non-spread and Spread) and pin 17,18 (SRC[T/C]0 or
100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
53
REF0/FSC
I/O
Fixed 14.318-MHz clock output / 3.3V-tolerant input for CPU frequency
selection
Refer to DC Electrical Specification Table for VilFS_C, VimFS_C and VihFS_C
specifications
54
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
55
PCI_STP#
I, PU
3.3V LVTTL input for PCI_STP# active LOW.
56
PCI2/SEL_CLKREQ# I/O, PD
SE
Fixed 33-MHz clock output/3.3V-tolerant input for CLKREQ# pins 32 and 33
selection
(sampled on the VTT_PWRGD# assertion).
0 = CLKREQ#[A:B] functionality
1 = SRC[T/C]9 functionality
Pin Descriptions (continued)
Pin No.
Name
Type
Description
FCTSEL1 FCTSEL0 PIN 14
PIN 15
PIN 17
PIN 18
0
0
DOT96T
DOT96C
100MT_SST 100MC_SST
0
1
DOT96T
DOT96C
SRCT0
SRCC0
1
0
27M_non spread 27M_Spread SRCT0
SRCC0
1
1
OFF Low
TBD
SRCT0
SRCC0
Table 1. Frequency Select Table FSA, FSB and FSC
FSC
FSB
FSA
CPU
SRC
PCIF/PCI
27MHz
REF0
DOT96
USB
1
0
1
100 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
0
1
133 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
1
166 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
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