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CY28517ZXCT Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY28517ZXCT
Description  PCI Express Clock Generator
Download  12 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY28517ZXCT Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY28517
Document #: 001-42225 Rev. *A
Page 3 of 12
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power up, and therefore use of this
interface is optional. Clock device register changes are normally
made upon system initialization, if any are required. This is a
RAM based technology which does not keep its value when
power is off or during a power transition.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write or read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the system
controller can access individually indexed bytes. The offset of the
indexed byte is encoded in the command code, as described in
Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 on page 4 outlines the corresponding byte write
and byte read protocol. The slave receiver address is 11010010
(D2h) for write and 11010011(D3h) for read.
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8-bit ‘00000000’ stands for block
operation
11:18
Command Code – 8-bit ‘00000000’ stands for block
operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29:36
Data byte 0 – 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 – 8 bits
30:37
Byte count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
Data Byte N/Slave Acknowledge...
39:46
Data byte from slave – 8 bits
Data Byte N – 8 bits
47
Acknowledge
Acknowledge from slave
48:55
Data byte from slave – 8 bits
Stop
56
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
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