CY29775
Document #: 38-07480 Rev. *A
Page 2 of 11
Pinouts
Figure 1. Pin Diagram - 52-Pin 1.0-mm TQFP package
Table 1. Pin Definition - 52-Pin 1.0-mm TQFP package
Pin[1]
Name
IO
Type
Description
9
TCLK0
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
16, 18, 21,
23, 25
QA(4:0)
O
LVCMOS
Clock output bank A
32, 34, 36,
38, 40
QB(4:0)
O
LVCMOS
Clock output bank B
44, 46, 48,
50
QC(3:0)
O
LVCMOS
Clock output bank C
29
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation.
This input must be at the same voltage rail as input reference clock.
See Table 2 on page 4.
2
MR#/OE
I, PU
LVCMOS
Output enable/disable input. See Table 3 on page 4.
3
CLK_STP#
I, PU
LVCMOS
Clock stop enable/disable input. See Table 3 on page 4.
6
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Table 3 on page 4.
8
TCLK_SEL
I, PD
LVCMOS
Reference select input. See Table 3 on page 4.
11, 52
VCO_SEL(1,0)
I, PD
LVCMOS
VCO divider select input. See Tables 3, 4 and 5.
7, 4, 5
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C). See Table 4 on page 4.
20, 14
FB_SEL(1,0)
I, PD
LVCMOS
Feedback dividers select inputs. See Table 5 on page 5.
17, 22, 26
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks[2,3]
33, 37, 41
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks[2,3]
VSS
MR#/OE
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
VCO_SEL1
VDD
AV DD
VSS
QB1
V DDQB
QB2
VSS
QB3
V DDQB
QB4
FB_IN
VSS
FB_OUT
V DDFB
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29775
Notes
1. PU = Internal pull up, PD = Internal pull down
2. A 0.1-
μF bypass capacitor must be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high
frequency filtering characteristics is cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
