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CY62177DV20LL-70BAI Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY62177DV20LL-70BAI
Description  32-Mbit (2M x 16) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62177DV20LL-70BAI Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY62177DV20 MoBL2™
Document #: 001-44018 Rev. **
Page 5 of 11
Switching Characteristics
Over the Operating Range [9]
Parameter
Description
70 ns
Unit
Min
Max
Read Cycle
tRC
Read Cycle Time
70
ns
tAA
Address to Data Valid
70
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low-Z[10]
5ns
tHZOE
OE HIGH to High-Z[10, 11]
25
ns
tLZCE
CE1 LOW and CE2 HIGH to Low-Z
[10]
10
ns
tHZCE
CE1 HIGH and CE2 LOW to High-Z
[10, 11]
25
ns
tPU
CE1 LOW and CE2 HIGH to Power Up
0
ns
tPD
CE1 HIGH and CE2 LOW to Power Down
70
ns
tDBE
BLE/BHE LOW to Data Valid
70
ns
tLZBE
BLE/BHE LOW to Low-Z[10]
5ns
tHZBE
BLE/BHE HIGH to High-Z[10, 11]
25
ns
Write Cycle[12]
tWC
Write Cycle Time
70
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
60
ns
tAW
Address Setup to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
45
ns
tBW
BLE/BHE LOW to Write End
60
ns
tSD
Data Setup to Write End
30
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High-Z[10, 11]
25
ns
tLZWE
WE HIGH to Low-Z[10]
10
ns
Notes
9. Test conditions are based on signal transition time of 2 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL.
10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state.
12. The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
[+] Feedback


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