FLEx18™ 3.3V 64K/128K/256K/512K x 18
Synchronous Dual-Port RAM
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06077 Rev. *C
Revised May 5, 2005
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 256-ball FBGA (1 mm pitch)
• Counter wrap-around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
• Seamless migration to next-generation dual-port family
Functional Description
The FLEx18
™ family includes 1-Mbit, 2-Mbit, 4-Mbit and
9-Mbit pipelined, synchronous, true dual-port static RAMs that
are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD09S18V device in this family has limited features.
Please see Address Counter and Mask Register Operations
on page 5 for details.
Seamless Migration to Next Generation Dual Port Family
Cypress offers a migration path for all devices in this family to
the next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details.
Table 1. Product Selection Guide
Density
1 Mbit
(64K x 18)
2 Mbit
(128K x 18)
4 Mbit
(256K x 18)
9 Mbit
(512K x 18)
Part Number
CYD01S18V
CYD02S18V
CYD04S18V
CYD09S18V
Max. Speed (MHz)
167
167
167
133
Max. Access Time – Clock to Data (ns)
4.0
4.0
4.0
4.7
Typical operating current (mA)
225
225
225
270
Package
256FBGA
(17 mm x 17 mm)
256FBGA
(17 mm x 17 mm)
256FBGA
(17 mm x 17 mm)
256FBGA
(17 mm x 17 mm)
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