PRELIMINARY
CYU01M16SFCU
MoBL3™
Document #: 38-05603 Rev. *B
Page 5 of 12
AC Test Loads and Waveforms
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
VTH
Equivalent to:
THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameters
1.8V (VCC)Unit
R1
14000
Ω
R2
14000
Ω
RTH
7000
Ω
VTH
0.90
V
Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14]
Parameter
Description
70 ns
Unit
Min.
Max.
Read Cycle
tRC [13]
Read Cycle Time
70
40000
ns
tCD
Chip Deselect Time CE1 = HIGH or
CE2 = LOW, BLE/BHE High Pulse Time
15
ns
tAA
Address to Data Valid
70
ns
tOHA
Data Hold from Address Change
5
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low Z[10, 11, 12]
5ns
tHZOE
OE HIGH to High Z[10, 11, 12]
25
ns
tLZCE
CE1 LOW and CE2 HIGH to Low Z[10, 11, 12]
10
ns
tHZCE
CE1 HIGH and CE2 LOW to High Z[10, 11, 12]
25
ns
tDBE
BLE/BHE LOW to Data Valid
70
ns
tLZBE
BLE/BHE LOW to Low Z[10, 11, 12]
5ns
tHZBE
BLE/BHE HIGH to High Z[10, 11, 12]
25
ns
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ.)/2, input pulse levels
of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
10. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high -impedence state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. If invalid address signals shorter than min.tRC are continuously repeated for 40
µs, the device needs a normal read timing (tRC) or needs to enter standby
state at least once in every 40
µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable (CE1 or CE2) controlled. That is, the addresses must be stable prior to Chip
Enable going active.
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