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CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 3 of 29
Transmit Path Block Diagram
TXRATE
Character-Rate Clock
Bit-Rate Clock
HML
TXCLKA
HML
HML
TXCLKB
TXCLKC
TXDA[0..9]
TXOPA
TXDB[0..9]
TXOPB
TXDC[0..9]
TXOPC
TXPERA
TXPERB
TXPERC
HML
TXCLKD
TXDD[0..9]
TXOPD
11
TXPERD
11
11
11
11
11
11
11
11
11
11
11
10
10
10
10
OUTA+
OUTA–
TXLBA
OUTB+
OUTB–
TXLBB
OUTC+
OUTC–
TXLBC
OUTD+
OUTD–
TXLBD
SPDSEL
TXRST
PARCTL
Parity Control
REFCLK+
REFCLK–
Transmit PLL
Clock Multiplier
TXCLKO+
TXCLKO–
TXCKSEL
BISTLE
OELE
= Internal Signal
BIST Enable
Latch
Output
Enable
4
8
Latch
BOE[7..0]
RBIST[A..D]
TXLBC