CYV15G0401DXB
CYP15G0401DXB
CYW15G0401DXB
Document #: 38-02002 Rev. *L
Page 10 of 53
Transmit Path Mode Control
TXMODE[1:0] Three-level Select [5]
static control inputs
Transmit Operating Mode. These inputs are interpreted to select one of nine
operating modes of the transmit path. See Table 3 for a list of operating modes.
Receive Path Data Signals
RXDA[7:0]
RXDB[7:0]
RXDC[7:0]
RXDD[7:0]
LVTTL Output,
synchronous to the
selected RXCLKx
↑ output
(or REFCLK
↑ input[4]
when RXCKSEL = LOW)
Parallel Data Output. These outputs change following the rising edge of the selected
receive interface clock.
When the Decoder is enabled (DECMODE = HIGH or MID), these outputs represent
either received data or special characters. The status of the received data is repre-
sented by the values of RXSTx[2:0].
When the Decoder is bypassed (DECMODE = LOW), RXDx[7:0] become the higher
order bits of the 10-bit received character. See Table 18 for details.
RXSTA[2:0]
RXSTB[2:0]
RXSTC[2:0]
RXSTD[2:0]
LVTTL Output,
synchronous to the
selected RXCLKx
↑ output
(or REFCLK
↑ input[4]
when RXCKSEL = LOW)
Parallel Status Output. These outputs change following the rising edge of the
selected receive interface clock.
When the Decoder is bypassed (DECMODE = LOW), RXSTx[1:0] become the two
low-order bits of the 10-bit received character, while RXSTx[2] = HIGH indicates the
presence of a Comma character in the Output Register. See Table 18 for details.
When the Decoder is enabled (DECMODE = HIGH or MID), RXSTx[2:0] provide
status of the received signal. See Table 20, 23 and 24 for a list of Receive Character
status.
RXOPA
RXOPB
RXOPC
RXOPD
three-state, LVTTL
Output, synchronous to
the selected
RXCLKx
↑ output
(or REFCLK
↑ input[4]
when RXCKSEL = LOW)
Receive Path Odd Parity. When parity generation is enabled (PARCTL
≠ LOW), the
parity output at these pins is valid for the data on the associated RXDx bus bits. When
parity generation is disabled (PARCTL = LOW) these output drivers are disabled
(High-Z).
Receive Path Clock and Clock Control
RXRATE
LVTTL Input, static control
input, internal pull-down
Receive Clock Rate Select. When LOW, the RXCLKx
± recovered clock outputs are
complementary clocks operating at the recovered character rate. Data for the
associated receive channels should be latched on the rising edge of RXCLKx+ or
falling edge of RXCLKx–.
When HIGH, the RXCLKx± recovered clock outputs are complementary clocks
operating at half the character rate. Data for the associated receive channels should
be latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When REFCLK± is selected to clock the output registers (RXCKSELx = LOW),
RXRATEx is not interpreted. The RXCLKA± and RXCLKC± output clocks will follow
the frequency and duty cycle of REFCLK±.
FRAMCHAR Three-level Select [5],
static control input
Framing Character Select. Used to select the character or portion of a character
used for character framing of the received data streams. When MID, the Framer looks
for both positive and negative disparity versions of the eight-bit Comma character.
When HIGH, the Framer looks for both positive and negative disparity versions of the
K28.5 character. Configuring FRAMCHAR to LOW is reserved for component test.
RFEN
LVTTL Input,
asynchronous,
internal pull-down
Reframe Enable for All Channels. Active HIGH. When HIGH, the framers in all four
channels are enabled to frame per the presently enabled framing mode as selected
by RFMODE and selected framing character as selected by FRAMCHAR.
RXMODE[1:0] Three-level Select [5],
static control inputs
Receive Operating Mode. These inputs are interpreted to select one of nine
operating modes of the receive path. See Table 14 for details.
Pin Descriptions (continued)
CYP(V)(W)15G0401DXB Quad HOTLink II Transceiver
Pin Name
I/O Characteristics
Signal Description
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