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W255
Document #: 38-07255 Rev. *D
Page 7 of 10
Layout Example for DDR 2.5V Only
FB
+2.5V Supply
C4
10 mF
0.005 mF
G
G
VDDQ2
C3
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46
45
44
43
42
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G
V
G = VIA to GND plane layer
V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Ceramic Caps C3 = 10–22 µF
C4 = 0.005 µF
FB = Dale ILB1206 - 300 (300
Ω @ 100 MHz) or TDK ACB 2012L-120
All bypass caps = 0.1
µF ceramic
G
V
G
V
G
V
G
V
G
V
G
V
G
V
G
V
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G