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ZM7332G-65505Y-T2 Datasheet(PDF) 5 Page - Power-One |
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ZM7332G-65505Y-T2 Datasheet(HTML) 5 Page - Power-One |
5 / 32 page ZM7300G Series Digital Power Manager Data Sheet REV. 3.3 NOV 26, 2007 www.power-one.com Page 5 of 32 8.3 Signal Specifications Parameter Conditions/Description Min Nom Max Units SYNC/DATA Line SDpu SD pull up resistor 5 kΩ SDthrL SD input low voltage threshold 0.31·VDD 0.52·VDD V SDthrH SD input high voltage threshold 0.45·VDD 0.81·VDD V SDhys SD input hysteresis 0.37 1.1 V SDsink SD sink capability (VSD=0.5V) 30 mA Freq_sd Clock frequency 450 550 kHz Tsynq Sync pulse duration 22 28 % of clock cycle T0 Data=0 pulse duration 72 78 % of clock cycle Interrupt Inputs (INT_N[3:0]) Rpu3 Pull up resistor 30 kΩ VthrL3 Input low voltage threshold 0.31·VDD 0.52·VDD V VthrH3 Input high voltage threshold 0.45·VDD 0.81·VDD V Vhys3 Input hysteresis 0.37 1.1 V ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs Rpu1 Pull up resistor 20 50 kΩ VthrL1 Input low voltage -0.5 0.2·VDD V VthrH1 Input high voltage 0.7·VDD VDD+0.5 V HRES_N Input Rpu2 HRES_N pull up resistor 30 60 kΩ VthrL2 HRES_N input low voltage -0.5 0.2·VDD V VthrH2 HRES_N input high voltage 0.9·VDD VDD+0.5 V Inputs/Outputs (OK_A, OK_B, OK_C, OK_D) OKpu OK pull up resistor 5 kΩ OKthrL OK input low voltage threshold 0.31·VDD 0.52·VDD V OKthrH OK input high voltage threshold 0.45·VDD 0.81·VDD V OKhys OK input hysteresis 0.37 1.1 V OKsink OK sink capability (VOK=0.5V) 30 mA Enable Outputs (EN[3:0]) VEN EN logic level enabled High VEN EN logic level disabled Low ENpu EN pull up resistor 30 kΩ ENsink EN sink current, VEN=0.5V 5 mA |
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